LM65645 Footprint Repair


Repair the LM65645SRZTRQ1 library part
Edit only this active part project. Verify against TI official datasheet https://www.ti.com/lit/ds/snvsch2a/snvsch2a.pdf and repair the footprint so it is safe in consuming boards and passes overlapping-copper/auto-route precheck.
Required outcomes
  • Keep exactly 21 schematic terminals: pins 1–20 per TI Table 5-1 plus exposed DAP represented as terminal/pad 21 GND.
  • Official pinout is NC1, PG2, FB3, VCC4, MODE/SYNC5, RT6, EN/UVLO7, NC8, PGND1 9, NC10, VIN1 11, NC12, SW1 13, SW2 14, BOOT15, NC16, VIN2 17, NC18, PGND2 19, BIAS20, DAP/EP21 GND. Do not invent AGND or move PG; TI Rev A explicitly has PG=2 and FB=3.
  • Remove optional thermal vias/pads 22–27 and every other unbound mount pad or imported copper land that overlaps electrical pads. Optional PCB thermal vias are board features, not component terminals or floating footprint pads.
  • Preserve the official RZT0020A copper land pattern and DAP copper. DAP must be the sole exposed-pad copper terminal and be GND-capable.
  • Inspect all pad geometry and ensure no separate un-netted imported polygon/pad overlaps VIN1, VIN2, EN/UVLO, NC1, or DAP.
  • Verify symbol pin names/numbers/types and footprint pad bindings after repair. Run relevant part checks and report exact changes.
Do not approximate dimensions; use the official TI package drawing or the existing correct terminal pads, deleting only defective duplicate/unbound geometry.
I’m blocked because your access to this part project is view-only, so I can’t repair or validate-save the footprint. Please fork the part into a project you own or grant edit access, then resend this request; I’ll preserve the official RZT0020A lands, remove pads/thermal vias 22–27 and overlapping unbound copper, verify all 21 terminal bindings, and run the part checks.
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Name
Pin #
Type
Part Type
Pin Description
Terminal Order
NC1
1
Not Connected
Terminal
No connect; leave floating.
PG
2
Open Collector
Terminal
Power-good open-drain output; low when VOUT is outside regulation window; use pullup.
FB
3
Input
Terminal
Feedback/configuration pin; GND selects 3.3 V fixed, VCC selects 5 V fixed, divider selects adjustable output; 0.8 V threshold.
VCC
4
Power Out
Terminal
Internal LDO output for control circuits; no external load except logic pullups; bypass to GND with 1 uF.
MODE_SYNC
5
Input
Terminal
Mode and synchronization input; low selects AUTO mode; high or clock selects FPWM/synchronization.
RT
6
Input
Terminal
Switching-frequency programming pin; tie to VCC for 400 kHz, GND for 2.2 MHz, or resistor to GND for 300 kHz to 2.2 MHz; do not float.
EN_UVLO
7
Input
Terminal
Precision enable and UVLO input; high enables converter, low disables; can connect to VIN or resistor divider; do not float.
NC2
8
Not Connected
Terminal
No connect; leave floating.
PGND1
9
Ground
Terminal
Power ground for low-side MOSFET; connect to system ground and VIN1 bypass capacitor return.
NC
10
Not Connected
Terminal
No connect; leave floating.
VIN1
11
Power In
Terminal
Input supply; connect bypass capacitors from VIN1 to PGND1.
NC
12
Not Connected
Terminal
No connect; leave floating.
SW1
13
Power Out
Terminal
Switch node; connect to output inductor.
SW2
14
Power Out
Terminal
Switch node; connect to output inductor.
BOOT
15
Power In
Terminal
High-side driver bootstrap supply; connect 100 nF capacitor between BOOT and SW.
NC
16
Not Connected
Terminal
No connect; leave floating.
VIN2
17
Power In
Terminal
Input supply; connect bypass capacitors from VIN2 to PGND2.
NC
18
Not Connected
Terminal
No connect; leave floating.
PGND2
19
Ground
Terminal
Power ground for internal low-side MOSFET; connect to system ground and VIN2 bypass capacitor return.
BIAS
20
Power In
Terminal
Input to internal voltage regulator; connect to VOUT or 3.3 V to 30 V bias when allowed; tie to GND if VOUT >30 V and no external bias.
DAP
21
Ground
Terminal
Exposed thermal pad; connect to system ground copper for electrical, thermal, and mechanical performance.

LM65645SRZTRQ1