Part Audit Review
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A datasheet URL is already populated, so no link update is required. I’m now validating that document against Renesas’ official package and pin data.
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Part Audit Report
Part Audit Report
Scope
Audit of the ICM7555IPA part metadata, schematic symbol, footprint, and pin definitions against the official Renesas ICM7555/ICM7556 datasheet (FN2867 Rev.10.01, March 5, 2020).
Official source: https://www.renesas.com/en/document/dst/icm7555-icm7556-datasheet
Current Part Information
Ordering-Code Finding
The official 2020 Renesas ordering table lists ICM7555IPAZ, marked
Key Specifications7555 IPAZ, in an 8-lead Pb-free PDIP package (E8.3). It does not list ICM7555IPA as a current orderable code. ICM7555IPA is best treated as a legacy/non-RoHS identifier. The electrical pinout remains compatible, but sourcing metadata should distinguish the legacy code from the current ICM7555IPAZ code.Audit complete. The datasheet property was already populated, so it was not changed; the symbol pinout matches the Renesas datasheet.
Key flags:
ICM7555IPA is a legacy code—the current orderable PDIP is ICM7555IPAZ; package/mount metadata and pin descriptions/types are missing; and the footprint row spacing may differ from the 7.62 mm nominal specification. Full details are in the Part Audit Report.Fix metadata and pins
Verify footprint geometry
Use official datasheet
Check 3D alignment
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Part Audit Report
Scope
Audit of the ICM7555IPA part metadata, schematic symbol, footprint, and pin definitions against the official Renesas ICM7555/ICM7556 datasheet (FN2867 Rev.10.01, March 5, 2020).
Official source: https://www.renesas.com/en/document/dst/icm7555-icm7556-datasheet
Current Part Information
Table
| Field | Current value | Assessment |
|---|---|---|
| Manufacturer Part Number | ICM7555IPA | Legacy/non-RoHS ordering code; current Renesas ordering table lists ICM7555IPAZ |
| Manufacturer Name | Renesas | Acceptable; device originated with Intersil, now Renesas |
| Part Type | Integrated Circuit | Correct |
| Description | General Purpose Timers | Correct but very broad; “CMOS RC general-purpose timer” would be more precise |
| Pin count | 8 | Correct |
| Designator prefix | IC | Correct |
| Datasheet URL | Uploaded PDF hosted on Flux/Google storage | Present, so it was not changed; official Renesas URL is listed above |
| Package property | No explicit Package or Case Code property found | Metadata omission; footprint asset identifies the intended PDIP package |
| Mount property | No explicit Mount property found | Metadata omission; footprint is through-hole |
| Footprint asset | DIP794W56P254L958H533Q8N.kicad_mod | Consistent with 8-lead 7.62 mm-row PDIP |
| 3D model | ICM7555IPA.stp | Present; visual alignment was not independently measurable from available inspection data |
Ordering-Code Finding
The official 2020 Renesas ordering table lists ICM7555IPAZ, marked
7555 IPAZ, in an 8-lead Pb-free PDIP package (E8.3). It does not list ICM7555IPA as a current orderable code. ICM7555IPA is best treated as a legacy/non-RoHS identifier. The electrical pinout remains compatible, but sourcing metadata should distinguish the legacy code from the current ICM7555IPAZ code.Key Specifications
- Function: CMOS RC general-purpose timer; monostable and astable operation
- Functional supply range: 2 V to 18 V
- Static supply current: 40 uA typical at 5 V; 60 uA typical at 15 V
- Maximum oscillator frequency: 1 MHz typical
- Timing accuracy: 2% typical in specified monostable and astable tests
- Timing supply drift: 0.5%/V typical from 5 V to 15 V
- Trigger level: approximately 1/3 VDD
- Threshold/control level: approximately 2/3 VDD
- Output transition time: 75 ns typical rise and fall at the stated test load
- Package: E8.3 8-lead PDIP, JEDEC MS-001-BA
- Pin pitch: 2.54 mm
- Nominal row spacing: 7.62 mm
- Body length: 9.01 to 10.16 mm
- Body width: 6.10 to 7.11 mm (molded body); overall E dimension 7.62 to 8.25 mm
- Maximum package height: 5.33 mm
Pin Cross-Check
Table
| Pin | Symbol name | Datasheet name/function | Result |
|---|---|---|---|
| 1 | GND | GND, supply return | Match |
| 2 | ~TRIGGER | TRIGGER, active-low set/trigger input | Match; overbar notation correctly conveys active-low behavior |
| 3 | OUTPUT | OUTPUT, CMOS timing output | Match |
| 4 | ~RESET | RESET, active-low reset input | Match; overbar notation correctly conveys active-low behavior |
| 5 | CONTROL_VOLTAGE | CONTROL VOLTAGE, comparator-reference control input | Match |
| 6 | THRESHOLD | THRESHOLD, upper timing comparator input | Match |
| 7 | DISCHARGE | DISCHARGE, timing-capacitor discharge switch | Match |
| 8 | VDD | VDD, positive supply | Match |
The pin numbering and names are correct. However, every terminal currently has
Pin Type: Unspecified, and no Pin Description properties were found. Recommended pin types are: pin 1 Power/Ground, pins 2/4/5/6 Input, pin 3 Output, pin 7 Output or Open Collector/Open Drain equivalent, and pin 8 Power. Pin 7 is an internal low-side discharge switch and should not be modeled as a generic passive pin.Footprint Cross-Check
The footprint naming and inspected pad pattern are consistent with the E8.3 PDIP:
- 8 pads arranged as two rows of four
- 2.54 mm longitudinal pitch
- Approximately 7.936 mm inspected row-center spacing versus 7.62 mm nominal package lead-row spacing
- Approximately 1.158 mm pad diameter/width
- Rectangular pin-1 pad and round remaining pads
Footprint concern
The inspected row spacing appears to be about 7.936 mm, while the datasheet gives 7.62 mm BSC nominal lead-row spacing. DIP leads can be formed and footprints sometimes use slightly wider spacing, but this is not a direct match to the package nominal. The footprint file name also contains
W56, whose meaning is unclear from the available data. Exact drill diameter, plated-hole size, courtyard, fab outline, and silkscreen geometry were not exposed by the inspection interface, so full IPC/manufacturability validation was not possible.Mismatches and Risks
- MPN status mismatch: Current metadata says
ICM7555IPA; the current official Renesas orderable PDIP code isICM7555IPAZ. - Missing package metadata: No explicit
Package or Case Code = E8.3 / PDIP-8property was found. - Missing mount metadata: No explicit
Mount = Through Holeproperty was found. - Pin electrical types unspecified: All eight symbol terminals are
Unspecified, reducing ERC value. - Pin descriptions absent: Functional descriptions are not encoded on the terminals.
- Potential footprint row-spacing discrepancy: Inspected spacing is approximately 7.936 mm rather than the datasheet’s 7.62 mm BSC nominal.
- Datasheet link provenance: A datasheet is present, but it is an uploaded storage copy rather than the durable official Renesas page URL. Per the request, it was not replaced because the property was not empty.
Overall Verdict
The symbol’s pin numbering and functional names are correct, and the footprint is recognizably an 8-pin through-hole PDIP with correct pin pitch and pin-1 marking. The main issues are sourcing/metadata quality, unspecified pin electrical types/descriptions, and a possible footprint row-spacing mismatch that should be checked directly in the footprint editor before production use.
Scope
Current Part Information
Ordering-Code Finding
Key Specifications
Pin Cross-Check
Footprint Cross-Check
Footprint concern
Mismatches and Risks
Overall Verdict
