Hirose Connector Audit
Thought for 15 sec
I found the project’s footprint asset and part metadata, but the indexed PCB data does not expose the full per-pad rule details for the KiCad footprint pads — it only confirms that pads
1–30 exist under footprint asset F-ER830P08SV2H, and that the uploaded footprint file is ER830P08SV2H.kicad_mod.Project part identity:
- MPN:
ER8-30P-0.8SV-2H - Manufacturer: Hirose
- Connector: ER8 series, 30-position, 2-row, 0.8 mm pitch board-to-board header
- Footprint asset:
ER830P08SV2H.kicad_mod - 3D model:
ER8-30P-0.8SV-2H.stp
From the Hirose/RS data fetched for this exact MPN, the manufacturer’s recommended PCB layout is:
- 30 contacts, 2 rows
- Pitch: 0.8 mm
- 15 contacts per row
- Contact span C: 11.2 mm
- Mounting-hole span B: 14.8 mm
- Mounting holes:
2 × Ø1.45 ±0.08 mm, non-plated through holes - Connector outline / keepout A: 18.0 mm
- Body/outline width reference: 5.6 mm
- Pin 1 shown at left side of layout
- Pin 2 shown on lower row
Assuming the footprint origin is centered, the expected 0.8 mm-pitch pad-center coordinates for the 30 signal pads are:
Table
| Pad | X mm | Row / expected Y |
|---|---|---|
| 1 | -5.6 | upper row |
| 2 | -5.6 | lower row |
| 3 | -4.8 | upper row |
| 4 | -4.8 | lower row |
| 5 | -4.0 | upper row |
| 6 | -4.0 | lower row |
| 7 | -3.2 | upper row |
| 8 | -3.2 | lower row |
| 9 | -2.4 | upper row |
| 10 | -2.4 | lower row |
| 11 | -1.6 | upper row |
| 12 | -1.6 | lower row |
| 13 | -0.8 | upper row |
| 14 | -0.8 | lower row |
| 15 | 0.0 | upper row |
| 16 | 0.0 | lower row |
| 17 | 0.8 | upper row |
| 18 | 0.8 | lower row |
| 19 | 1.6 | upper row |
| 20 | 1.6 | lower row |
| 21 | 2.4 | upper row |
| 22 | 2.4 | lower row |
| 23 | 3.2 | upper row |
| 24 | 3.2 | lower row |
| 25 | 4.0 | upper row |
| 26 | 4.0 | lower row |
| 27 | 4.8 | upper row |
| 28 | 4.8 | lower row |
| 29 | 5.6 | upper row |
| 30 | 5.6 | lower row |
Expected mounting-hole centers, assuming centered origin:
Table
| Hole | X mm | Y mm | Geometry |
|---|---|---|---|
| MH1 | -7.4 | 0 | Ø1.45 mm NPTH |
| MH2 | +7.4 | 0 | Ø1.45 mm NPTH |
Expected outline / placement references:
- Overall connector/avoid area length: 18.0 mm
- Hole-to-hole span: 14.8 mm
- Contact-center span: 11.2 mm
- Pin 1 orientation: left side of connector; pin 1 on the upper row, pin 2 on the lower row per manufacturer drawing orientation.
Likely manufacturing mismatch flags against a correct 0.8 mm-pitch two-row connector:
- Project index did not expose pad size/shape/layer details, so I could not verify exact copper pad width/length from the indexed footprint.
- If the actual footprint pad centers differ from the
-5.6 mm … +5.6 mmsequence at 0.8 mm pitch, the connector will not solder correctly. - If MH1/MH2 are not Ø1.45 mm NPTH at approximately
±7.4 mm, the plastic locating pegs may not fit. - If the footprint treats the mounting holes as plated copper pads instead of non-plated mechanical holes, that would be a likely fabrication mismatch.
- If pin 1 is not on the left-side upper row relative to the manufacturer’s recommended layout, the connector may be mirrored or rotated incorrectly.
- The project metadata has a suspicious package value: “Package or Case Code: TO”, which does not match this connector package and should not be relied on for manufacturing.
Thought for 4 sec
Audit complete. The MPN and 30-pin count are correct, but I flagged several issues:
- Package code
TOis incorrect for this Hirose SMT board-to-board connector. - All 30 symbol pins lack descriptions and use
Unspecifiedinstead of passive pin types. - The Datasheet property already exists, so it was not changed; however, it points to an RS product page rather than the official Hirose product documentation.
- The footprint has pads 1–30 and two mounting holes, but exact pad dimensions and hole plating were not exposed for definitive verification. Manufacturer requirements include 0.8 mm pitch, 2 × Ø1.45 mm NPTH holes at 14.8 mm spacing, and an 18.0 × 5.6 mm connector envelope.
Key ratings: 0.5 A/contact, 100 VAC, 50 mΩ maximum contact resistance, 1000 MΩ minimum insulation resistance, 300 VAC withstand, 100 mating cycles, 85 Ω differential impedance, and PCIe Gen.4/16 Gbps support. Hirose sources conflict on the upper operating temperature: the specification sheet states +85 °C, while the current product page states +125 °C.
Fix metadata and pins
Update Datasheet URL
Correct pin metadata
Verify footprint geometry
File quality issue
