Pin Function Grouping


Power, Control, and JTAG are set; I’m applying the same ordering/orientation rules to the Digital I/O and Ground groups now.
I hit a tool namespace hiccup on the bulk update and corrected course; continuing with the direct schematic edit path so the properties are applied in-place.
Updated and verified all 84 pins.
Mapping applied:
  • Power: Terminal Order 1, Top
  • Control: Terminal Order 3, Right
  • JTAG: Terminal Order 5, Left
  • Digital I/O: Terminal Order 7, Right
  • Ground: Terminal Order 10, Bottom
Open item:
  • Since only Left/Right were allowed for the three non-power/non-ground groups, one side necessarily repeats.
Suggested next step:
  1. Ask me to visually reorganize the symbol using these section/order/orientation settings.
Arrange review export
Arrange symbol visually
Run pin review
Export pin mapping
Fix side distribution

3 · VCCINT26 · VCCIO43 · VCCINT13 · VCCIO38 · VCCIO66 · VCCIO53 · VCCIO78 · VCCIOINPUT/OE2/(GCLK2) · 2INPUT/GLCRN · 1INPUT/GCLK1 · 83INPUT/OE1 · 8423 · I/O/TMS_2362 · I/O/TCK_6271 · I/O/TDO_7114 · I/O/TDI_14I/O_69 · 69I/O_34 · 34I/O_25 · 25I/O_64 · 64I/O_48 · 48I/O_30 · 30I/O_79 · 79I/O_45 · 45I/O_18 · 18I/O_22 · 22I/O_29 · 29I/O_41 · 41I/O_58 · 58I/O_52 · 52I/O_21 · 21I/O_49 · 49I/O_17 · 17I/O_44 · 44I/O_31 · 31I/O_24 · 24I/O_20 · 20I/O_70 · 70I/O_11 · 11I/O_56 · 56I/O_6 · 6I/O_61 · 61I/O_37 · 37I/O_46 · 46I/O_68 · 68I/O_40 · 40I/O_77 · 77I/O_27 · 27I/O_36 · 36I/O_81 · 81I/O_39 · 39I/O_74 · 74I/O_4 · 4I/O_15 · 15I/O_63 · 63I/O_76 · 76I/O_10 · 10I/O_50 · 50I/O_12 · 12I/O_35 · 35I/O_54 · 54I/O_51 · 51I/O_9 · 9I/O_67 · 67I/O_5 · 5I/O_73 · 73I/O_57 · 57I/O_16 · 16I/O_33 · 33I/O_8 · 8I/O_75 · 75I/O_60 · 60I/O_80 · 80I/O_65 · 65I/O_55 · 55I/O_28 · 28GND · 19GND · 82GND · 47GND · 72GND · 7GND · 42GND · 59GND · 32

EPM7128SLC84-10N

EPM7128SLC84-10N thumbnail