Pin Grouping by Function


Grouped the DRV8718S-Q1 pins by datasheet-backed function and verified all 57 terminals are assigned exactly once. I set Section = Pin Group for each pin, added orientations/order, pin types, and concise pin descriptions.
Open items:
  • None.
Suggested next steps:
  • Review the rendered parametric symbol layout visually.
  • If desired, I can split these into separate sub-symbols, e.g. Power/Ground, SPI/Control, Gate Drive 1–4, Gate Drive 5–8.
  • Make the functional group more general.
  • Add a Section property to all pins, and apply the same value used in the Pin Group property to each pin's Section property.
Assign a Terminal Order from 1 to 10, starting with Power. Power should be Terminal Order 1, and Ground should be last, Terminal Order 10. For Orientation, set Power to "Top" and Ground to "Bottom." For the remaining sections/groups, you may decide the Terminal Order and Orientation yourself. For Orientation, distribute them between "Left" and "Right" — don't put everything on one side. Each group/section should have a different orientation.
I’ll generalize the pin groups, mirror each Pin Group into Section, and set group-level Terminal Order/Orientation with Power first and Ground last.
Updated all pins to broader functional groups and verified Section matches Pin Group on every terminal.
Open items:
  • None.
Suggested next steps:
  • Review the symbol rendering after the grouping update.
  • Current group order is: Power=1, Interface=2, Control=3, Analog=4, Gate Drive=5, No Connect=9, Ground=10.
Review symbol and ERC
Review rendered symbol
Run ERC check
Use standard group names
Check footprint mapping

SH5
Pin Number
42
IN4
Pin Number
7
GND
Pin Number
57
DRVOFF/NFLT
Pin Number
9
SDO
Pin Number
3
DGND
Pin Number
54
SCLK
Pin Number
1
DVDD
Pin Number
55
AGND
Pin Number
11
PGND2
Pin Number
47
IN1
Pin Number
4
GH7
Pin Number
50
SDI
Pin Number
2
SP1
Pin Number
15
GL7
Pin Number
48
GH8
Pin Number
51
GL8
Pin Number
53
SH6
Pin Number
45
GH5
Pin Number
43
NSLEEP
Pin Number
8
BRAKE
Pin Number
14
IN3
Pin Number
6
GH6
Pin Number
44
SN1
Pin Number
16
NSCS
Pin Number
56
SH8
Pin Number
52
AREF
Pin Number
10
SH7
Pin Number
49
GL6
Pin Number
46
SO2
Pin Number
13
SO1
Pin Number
12
IN2
Pin Number
5
Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
SCLK
1
Input
Interface
Interface
Left
2
Serial clock input; internal pulldown
SDI
2
Input
Interface
Interface
Left
2
Serial data input; internal pulldown
SDO
3
Output
Interface
Interface
Left
2
Serial data output; push-pull output
IN1
4
Input
Control
Control
Right
3
Half-bridge and H-bridge control input; internal pulldown
IN2
5
Input
Control
Control
Right
3
Half-bridge and H-bridge control input; internal pulldown
IN3
6
Input
Control
Control
Right
3
Half-bridge and H-bridge control input; internal pulldown
IN4
7
Input
Control
Control
Right
3
Half-bridge and H-bridge control input; internal pulldown
NSLEEP
8
Input
Control
Control
Right
3
Device enable/sleep input, active low shutdown; internal pulldown
DRVOFF/NFLT
9
Bi-Directional
Control
Control
Right
3
Driver shutdown input or fault indicator output; internal pulldown
AREF
10
Power In
Power
Power
Top
1
External voltage reference and supply for current-sense amplifiers
AGND
11
Ground
Ground
Ground
Bottom
10
Analog/device ground
SO1
12
Output
Analog
Analog
Left
4
Shunt amplifier output 1
SO2
13
Output
Analog
Analog
Left
4
Shunt amplifier output 2
BRAKE
14
Input
Control
Control
Right
3
Powered-off braking input; internal pulldown
SP1
15
Input
Analog
Analog
Left
4
Amplifier positive input 1; connect to positive terminal of shunt resistor
SN1
16
Input
Analog
Analog
Left
4
Amplifier negative input 1; connect to negative terminal of shunt resistor
SP2
17
Input
Analog
Analog
Left
4
Amplifier positive input 2; connect to positive terminal of shunt resistor
SN2
18
Input
Analog
Analog
Left
4
Amplifier negative input 2; connect to negative terminal of shunt resistor
GL1
19
Output
Gate Drive
Gate Drive
Right
5
Low-side gate driver output 1
SH1
20
Input
Gate Drive
Gate Drive
Right
5
High-side source sense input 1
GH1
21
Output
Gate Drive
Gate Drive
Right
5
High-side gate driver output 1
GH2
22
Output
Gate Drive
Gate Drive
Right
5
High-side gate driver output 2
SH2
23
Input
Gate Drive
Gate Drive
Right
5
High-side source sense input 2

DRV8718SQRVJRQ1