Metadata: MPN and manufacturer are correct. Package is RRW0024A, 24-pin 3 × 3 mm WQFN plus exposed pad 25, 0.4 mm pitch.
Key specs: 3–20 V operation, 24 V absolute maximum, 5 A peak output, 200 kHz PWM, 10 MHz SPI/tSPI, 210 mΩ typical combined MOSFET on-resistance, and 3.3 V/100 mA AVDD output.
Pin numbering/names: All 25 terminals match the DRV8311P datasheet.
Datasheet: A URL was already set, so no property update was required.
Symbol issues: All terminals lack Pin Description metadata. OUTA/B/C and SOA/B/C are typed Unspecified; AVDD is incorrectly typed Power In despite being a regulator output.
Footprint: Perimeter pads, 0.4 mm pitch, 0.2 × 0.47 mm lands, and 1.9 mm exposed pad match TI’s nominal pattern. However, five extra 0.5 mm circular copper pads numbered 26–30 appear beneath the exposed pad without drill definitions; these do not match TI’s optional ~0.2 mm thermal vias and may cause incorrect mask/paste behavior.
I filed an internal part-quality report for the footprint and symbol metadata issues.
Current sense amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the CSAREF and AGND pins.
SOC
3
Output
Current sense amplifier output for OUTC.
SOB
4
Output
Current sense amplifier output for OUTB.
SOA
5
Output
Current sense amplifier output for OUTA.
CP
6
Power Out
Charge pump output. Connect a X5R or X7R, 0.1-µF, 16-V ceramic capacitor between the VCP and VM pins.
VIN_AVDD
7
Power In
Supply input for AVDD. Bypass to AGND with a X5R or X7R, 0.1-µF, VIN_AVDD-rated ceramic capacitor as well as a >=10-µF, VIN_AVDD-rated rated bulk capacitor between VIN_AVDD and PGND.
VM
8
Power In
Power supply for the motor. Connect to motor supply voltage. Connect a X5R or X7R, 0.1-µF VM-rated ceramic bypass capacitor as well as a >=10-µF, VM-rated bulk capacitor between VM and PGND. Additionally, connect a X5R or X7R, 0.1-µF, 16-V ceramic capacitor between the VM and CP pins.
PGND
9
Power In
Device power ground. Connect to system ground.
OUTA
10
Output
Half bridge output A. Connect to motor winding.
OUTB
11
Output
Half bridge output B. Connect to motor winding.
OUTC
12
Output
Half bridge output C. Connect to motor winding.
NC
13
Not Connected
No connect. Leave the pin floating.
AD1
14
Input
Only on tSPI device DRV8311P. Address selection for tSPI.
AD0
15
Input
Only on tSPI device DRV8311P. Address selection for tSPI.
AGND
16
Power In
Device analog ground. Connect to system ground.
AVDD
17
Power Out
3.3V regulator output. Connect a X5R or X7R, 0.7-µF to 7-µF, 6.3-V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 100 mA externally.
NC
18
Not Connected
No connect. Leave the pin floating.
PWM_SYNC
19
Input
Only on tSPI device DRV8311P. Connect to the MCU signal to synchronize the internally-generated PWM signals from DRV8311 to the MCU in PWM generation mode.
SCS_N
20
Input
Only on SPI (DRV8311S) and tSPI (DRV8311P) devices. Serial chip select. A logic low on this pin enables serial interface communication (SPI devices).
SDO
21
Output
Only on SPI (DRV8311S) and tSPI (DRV8311P) devices. Serial data output. Data is shifted out on the rising edge of the SCLK pin.
SDI
22
Input
Only on SPI (DRV8311S) and tSPI (DRV8311P) devices. Serial data input. Data is captured on the falling edge of the SCLK pin (SPI devices).
SCLK
23
Input
Only on SPI (DRV8311S) and tSPI (DRV8311P) devices. Serial clock input. Serial data is shifted out on the rising edge and captured on the falling edge of SCLK (SPI devices).