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BT840F Part Datasheet Review

Date: 2026-07-07

Source

Official datasheet found and attached to the part project:

Fanstel, BLE 5, Thread, Zigbee Modules, BT840/F/E/X/XE — Product Specifications, Ver. 1.22, Apr. 2022
URL: https://www.fanstel.com/s/BT840F_Product-Specifications-gyag.pdf

Part metadata reviewed

Table

Field	Project / library state	Datasheet / official source	Result
MPN	BT840F	BT840F	Match
Manufacturer	Initially blank in library search; project metadata set to Fanstel Corp.	Fanstel Corp.	Updated at project metadata level
Part type	Initially blank in library search; project metadata set to RF Transceiver	BLE 5 / Thread / Zigbee / IEEE 802.15.4 RF module based on nRF52840	Updated at project metadata level
Package	Project description included “1.27 Manufacturer Recommendations”; metadata set to Module	15 x 20.8 x 1.9 mm module, castellated + LGA pads	Needs footprint scale check; see below
Pin count	65 schematic terminals / 65 PCB pads	Pin-assignment table lists 65 pad locations	Match
Datasheet URL	Initially blank in library search; official URL attached to project metadata	Official Fanstel PDF	Updated at project metadata level

Note: Flux warned that part-style metadata fields such as Manufacturer Name, Part Type, Package or Case Code, and Datasheet URL are non-standard project-level properties in this editing context. The datasheet is now queryable from the part project, but a library search may still show the indexed Datasheet URL field as blank until the part metadata/index path is refreshed.

Key datasheet specs

Table

Spec	Value
Module	Fanstel BT840F / BlueNor BT840F series
SoC	Nordic nRF52840-QIAA, ARM Cortex-M4F, 64 MHz
Memory	1 MB Flash, 256 KB RAM
Radio	2.4 GHz multiprotocol transceiver
Protocols	BLE 5, Thread, Zigbee, IEEE 802.15.4, proprietary 2.4 GHz
BLE data rates	2 Mbps, 1 Mbps, 500 kbps, 125 kbps
IEEE 802.15.4 data rate	250 kbps
TX power	nRF52840 programmable +8 dBm to -20 dBm; BT840F max listed +8.8 dBm
Receiver sensitivity	-96 dBm at 1 Mbps, from nRF52840 spec cited in datasheet extraction
Operating voltage	Overall 1.7 V to 5.5 V; VDD 1.7 V to 3.6 V; VDDH 2.5 V to 5.5 V; VBUS 4.35 V to 5.5 V
Operating temperature	-40 °C to +85 °C
Module size	15 x 20.8 x 1.9 mm
Pins / pads	16 castellated edge pads plus LGA / ground / power pads, 65 pad locations in the pin table
Antenna placement	Antenna area should extend 9.8 mm beyond host PCB edge or ground plane; ground plane at least 5 mm from antenna area; external metal at least 30 mm from antenna area

Pin assignment actions applied

No pins were replaced. No pin numbers were changed. No pins were remapped. Only these properties were assigned on existing terminal components:

Pin Orientation
Section
Terminal Order

Power pins were ordered first. Ground pins were ordered last. Other pins were grouped by function according to the datasheet.

Full pin assignment table

Table

Order	Pin number	Schematic terminal	Section	Orientation	Datasheet function / note
1	9	VDD	Power	top	DC supply, 1.7 V to 3.6 V
2	F4	VDDH	Power	top	High-voltage power supply
3	F6	VBUS	Power	top	5 V USB supply for regulator
4	F5	DCCH	Power	top	DC-DC converter output
5	14	P0.18/RESET	Control	left	GPIO, configurable RESET pin
6	15	SWDCLK	Input	left	Serial Wire Debug clock input
7	16	SWDIO	Interface	right	Serial Wire Debug I/O
8	E4	D+	Interface	right	USB D+
9	E5	D-	Interface	right	USB D-
10	1	P0.26/SDA	Interface	right	GPIO, I2C SDA on EV-BT840
11	2	P0.27/SCL	Interface	right	GPIO, I2C SCL on EV-BT840
12	3	P0.00/XL1	Interface	right	GPIO, 32.768 kHz crystal connection
13	4	P0.01/XL2	Interface	right	GPIO, 32.768 kHz crystal connection
14	7	P0.09/NFC1	Interface	right	GPIO, NFC antenna connection
15	8	P0.10/NFC2	Interface	right	GPIO, NFC antenna connection
16	5	P0.02/AIN0	Analog	left	GPIO, analog input
17	6	P0.03/AIN1	Analog	left	GPIO, analog input
18	A3	P0.04/AIN2	Analog	left	GPIO, analog input
19	A4	P0.05/AIN3	Analog	left	GPIO, analog input
20	A1	P0.28/AIN4	Analog	left	GPIO, analog input
21	A2	P0.29/AIN5	Analog	left	GPIO, analog input
22	B2	P0.30/AIN6	Analog	left	GPIO / analog-capable nRF52840 pin
23	B3	P0.31/AIN7	Analog	left	GPIO / analog-capable nRF52840 pin
24	B4	P0.06	Digital	right	GPIO
25	A5	P0.07	Digital	right	GPIO
26	B5	P0.08	Digital	right	GPIO
27	11	P0.11	Digital	right	GPIO
28	E6	P0.12	Digital	right	GPIO
29	13	P0.13	Digital	right	GPIO
30	D4	P0.14	Digital	right	GPIO
31	C4	P0.15	Digital	right	GPIO
32	D3	P0.16	Digital	right	GPIO
33	C3	P0.17	Digital	right	GPIO
34	D2	P0.19	Digital	right	GPIO
35	E1	P0.20	Digital	right	GPIO
36	E2	P0.21	Digital	right	GPIO
37	C2	P0.22	Digital	right	GPIO
38	D1	P0.23	Digital	right	GPIO
39	C1	P0.24	Digital	right	GPIO
40	B1	P0.25	Digital	right	GPIO
41	12	P1.00	Digital	right	GPIO
42	D5	P1.01	Digital	right	GPIO
43	C5	P1.02	Digital	right	GPIO
44	B6	P1.03	Digital	right	GPIO
45	C6	P1.04	Digital	right	GPIO
46	D6	P1.05	Digital	right	GPIO
47	Z6	P1.06	Digital	right	GPIO
48	E0	P1.07	Digital	right	GPIO
49	A6	P1.08	Digital	right	GPIO
50	E3	P1.09	Digital	right	GPIO
51	Z5	P1.10	Digital	right	GPIO
52	Z0	P1.11	Digital	right	GPIO
53	Z1	P1.12	Digital	right	GPIO
54	Z2	P1.13	Digital	right	GPIO
55	Z3	P1.14	Digital	right	GPIO
56	Z4	P1.15	Digital	right	GPIO
57	10	GND::c8fa029f	Ground	bottom	Ground / VSS
58	A0	GND::5b6d7017	Ground	bottom	Ground / VSS
59	B0	GND::35f3feae	Ground	bottom	Ground / VSS
60	C0	GND::e2705752	Ground	bottom	Ground / VSS
61	D0	GND::66316182	Ground	bottom	Ground / VSS
62	F0	GND0	Ground	bottom	Ground pad
63	F1	GND1	Ground	bottom	Ground pad
64	F2	GND2	Ground	bottom	Ground pad
65	F3	GND3	Ground	bottom	Ground pad

Symbol / pin mapping cross-check

Result: No pin-number remaps were found in the schematic terminals checked against the datasheet pin table. The schematic has 65 terminal components and each terminal’s existing Pin Number matches the BT840F pin-assignment table for that signal name.

Notable details:

P0.30/AIN6 and P0.31/AIN7 are kept as named in the schematic. The extracted datasheet text labels B2/B3 as P0.30/P0.31 GPIO; the nRF52840 function naming supports analog capability, so these were placed in Analog rather than guessed as plain GPIO.
SWDCLK is assigned Input because the datasheet explicitly calls it “Serial Wire Debug clock input.”
SWDIO, USB, I2C, NFC, and 32.768 kHz crystal pins are grouped as Interface.

Pin description cross-check

The current terminal components do not appear to have populated Pin Description properties. The datasheet provides clear descriptions for most pins. Since the steering request explicitly limited the mutation to orientation, section, and terminal order, pin descriptions were not modified.

Footprint / mechanical cross-check

Datasheet mechanical references:

Module body: 15 x 20.8 x 1.9 mm
Castellated pad pitch: 1.10 mm
Castellated pad dimension shown: 0.70 mm
LGA circular pad diameter: 0.60 mm
LGA pitch: 1.50 mm
Larger ground/power pads such as F0-F3: 1.5 x 1.5 mm
Recommended antenna mounting: antenna area extends 9.8 mm beyond board/ground plane edge; ground plane at least 5 mm from antenna area; external metal at least 30 mm from antenna area

Current footprint observations:

The silk/body outline visually corresponds to approximately 15 x 20.8 mm, matching the datasheet body size.
PCB pad count is 65, matching the datasheet pin-location table.
Major footprint mismatch flagged: sampled pad geometry appears scaled 1000x too small in the computed PCB rules. Example: P0.26/SDA computed pad size is 0.0015 x 0.0007 mm at about x=-0.0065 mm, while the datasheet-scale pad should be around 1.5 x 0.7 mm and positioned in millimeters across the module body. GND0 similarly reports 0.0015 x 0.0015 mm instead of 1.5 x 1.5 mm.
The flat layout view shows the silk outline but not usable pad copper at visible scale, consistent with the computed pad-scale issue.
No explicit antenna keepout / host-ground clearance rule was found in the inspected layout data.

Mismatch / issue list

Table

Severity	Area	Finding	Recommended action
High	Footprint	Pad sizes and positions appear scaled 1000x too small relative to datasheet dimensions.	Regenerate or rescale the footprint pad geometry before using this part in a PCB.
Medium	RF layout	No antenna keepout / ground-clearance rule found.	Add antenna placement notes/keepout: 9.8 mm antenna extension, 5 mm ground clearance, 30 mm external metal clearance.
Medium	Metadata	Manufacturer Name, Part Type, Package, Datasheet URL were initially blank in library search.	Metadata was populated at project level; verify the published library index reflects it before reuse.
Low	Pin descriptions	Pin Description properties are not populated on terminals.	Optionally populate pin descriptions from the datasheet in a separate pass.

Verification status

Datasheet URL found from official Fanstel source and attached to the part project.
Pin orientation / section / terminal order assignments were applied and read back successfully.
No existing Pin Number values were changed.
No terminal components were replaced.
No pin-to-pad remapping was performed.

Source
Part metadata reviewed
Key datasheet specs
Pin assignment actions applied
Full pin assignment table
Symbol / pin mapping cross-check
Pin description cross-check
Footprint / mechanical cross-check
Mismatch / issue list
Verification status