Part Datasheet Review

I found the official Infineon PDF and updated the part’s Datasheet URL from the distributor page to the Infineon datasheet. I’m finishing the datasheet-vs-symbol/footprint review now.
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Part Datasheet Review: BSC010N04LS6ATMA1

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Review date: 2026-07-21 Official Infineon datasheet:
Done — I updated the part’s Datasheet URL to the official Infineon PDF and created the full review in Part Datasheet Review: BSC010N04LS6ATMA1.
Key findings: pins 1–8 match the datasheet source/gate/drain pinout, but pads 9–10 are ambiguous, all terminal metadata is unspecified/missing, and the footprint copper pads appear scaled ~1000× too small versus the Infineon PG-TDSON-8-FL land pattern.
Suggested next steps:
  • Fix/rebuild the footprint copper pad geometry from the Infineon boardpad drawing.
  • Decide whether pads 9–10 should be removed, marked non-electrical, or tied to Source/Drain.
  • Add Pin Type, Pin Description, Pin Group/Section, and terminal ordering metadata.
  • Re-run part review/DRC after corrections.
Fix part issues
Fix footprint geometry
Resolve extra pads
Add terminal metadata
Rerun part review
9
Pin Number
9
D_1
Pin Number
5
D_2
Pin Number
6
S_3
Pin Number
3
S_1
Pin Number
1
D_4
Pin Number
8
G
Pin Number
4
D_3
Pin Number
7
10
Pin Number
10
S_2
Pin Number
2

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Part Datasheet Review: BSC010N04LS6ATMA1
Review date: 2026-07-21
Source used
The project Datasheet URL property was updated from a Digi-Key product page to the official Infineon PDF above.
Available part information reviewed
  • Project/part name: BSC010N04LS6ATMA1
  • Manufacturer part number: BSC010N04LS6ATMA1
  • Manufacturer: Infineon
  • Part type: Transistor
  • Description: N-channel 40 V OptiMOS 6 power MOSFET, surface-mount PG-TDSON-8 / SuperSO8 FL family
  • Mount: Surface Mount
  • Designator prefix: Q
  • Package stated in context/description: PG-TDSON-8-6 / PG-TDSON-8 FL / SuperSO8 FL
  • Project terminal/pad count: 10 terminals/pads present in the Flux part project
Key datasheet specs
  • Device: OptiMOS 6 N-channel power MOSFET
  • Ordering part number: BSC010N04LS6ATMA1
  • Datasheet type/order code: BSC010N04LS6
  • Package: PG-TDSON-8 FL / SuperSO8 FL
  • Marking: 10N04LS6
  • Drain-source breakdown voltage: 40 V
  • Gate-source voltage: ±20 V
  • Continuous drain current: up to 100 A at TC = 25 °C per distributor/project description; datasheet also lists package/current ratings dependent on case/ambient and gate drive
  • Power dissipation: 150 W at TC = 25 °C; 3.0 W at TA = 25 °C on specified PCB thermal condition
  • Junction/storage temperature range: -55 °C to 175 °C
  • RDS(on): max 1.0 mΩ at VGS = 10 V, ID = 50 A; max 1.3 mΩ at VGS = 4.5 V, ID = 50 A from datasheet extraction
  • Gate threshold voltage: 1.2 V min, 2.0 V max at ID = 250 µA
  • Typical gate charge listed in project description: 67 nC
  • Package body dimensions from datasheet: D = 5.15 mm BSC, E = 6.15 mm BSC, pitch e = 1.27 mm BSC
Datasheet pinout vs schematic symbol

Table


PinProject terminalDatasheet functionResult
1S_1SourceMatch
2S_2SourceMatch
3S_3SourceMatch
4GGateMatch
5D_1DrainMatch
6D_2DrainMatch
7D_3DrainMatch
8D_4DrainMatch
99Not defined as an electrical pin in the 8-lead datasheet pinoutMismatch / ambiguous
1010Not defined as an electrical pin in the 8-lead datasheet pinoutMismatch / ambiguous
The 1-8 electrical pin mapping matches the datasheet. The extra pads 9 and 10 need clarification: if they model enlarged source/drain interconnection or thermal copper, they should be explicitly named and tied to the correct electrical function, not left as anonymous terminals.
Symbol metadata findings
  • All terminals currently have Pin Type = Unspecified.
  • Pin Description metadata is missing for all terminals.
  • Pin Group / Section metadata is missing for source, gate, and drain grouping.
  • Recommended grouping:
    • Pins 1-3: Source
    • Pin 4: Gate
    • Pins 5-8: Drain
    • Pads 9-10 if retained: assign to the correct Source/Drain exposed/interconnection function per the land pattern, or mark/remove as non-electrical/mechanical if appropriate.
Footprint cross-check
Datasheet package/land pattern dimensions are millimeter-scale:
  • Body: approximately 5.15 mm x 6.15 mm
  • Lead pitch: 1.27 mm
  • Boardpad values include dimensions such as 0.4 mm, 0.5 mm, 0.8 mm, 1.905 mm, 2.205 mm, 2.875 mm, 3.19 mm, and 3.325 mm.
Flux layout inspection found the footprint silkscreen/courtyard at plausible mm-scale extents, roughly ±2.5 mm and ±3.0 mm, but copper pads are computed at values such as:
  • Positions around ±0.001905 and ±0.003075 with unit reported as mm
  • Pad sizes around 0.0005 to 0.00441 mm
These pad values appear to be 1000x too small relative to the datasheet land pattern. Example comparisons:

Table


Expected datasheet-scale valueObserved project valueApparent error
1.905 mm0.001905 mm1000x too small
3.075 mm0.003075 mm1000x too small
0.5 mm0.0005 mm1000x too small
4.41 mm0.00441 mm1000x too small
Mismatches and risks flagged
  1. Critical footprint mismatch: copper pads appear scaled 1000x too small while silkscreen/courtyard is mm-scale. This would make the footprint unusable for PCB fabrication/assembly.
  2. Pin count ambiguity: datasheet electrical pinout is 8 pins, but the part project has 10 terminals/pads. Pads 9 and 10 are unnamed and not defined in the datasheet pinout.
  3. Missing terminal metadata: all pin types are unspecified; pin descriptions and pin groups are missing.
  4. Package naming should be normalized: current references are broadly consistent but should use exact wording such as PG-TDSON-8 FL / SuperSO8 FL, with PG-TDSON-8-6 if retaining distributor nomenclature.
  5. **No component review checks were available/matching in the current review output, so this was a manual datasheet cross-check rather than a passing automated part-review result.
  1. Rescale or rebuild the copper pad geometry against the Infineon PG-TDSON-8-FL boardpad drawing.
  2. Decide how pads 9 and 10 should be represented: remove them from the schematic symbol, mark as non-electrical/mechanical, or name/tie them to Source/Drain if they are required exposed/interconnection pads.
  3. Add terminal metadata: Pin Type, Pin Description, Pin Group, Section, and Terminal Order.
  4. Re-run part review / DRC after the footprint and terminal metadata are corrected.
  • Source used

  • Available part information reviewed

  • Key datasheet specs

  • Datasheet pinout vs schematic symbol

  • Symbol metadata findings

  • Footprint cross-check

  • Mismatches and risks flagged

  • Recommended next fixes

Assets

kicad_mod

BSC010N04LS6ATMA1

BSC010N04LS6ATMA1.kicad_modFootprint
BSC010N04LS6ATMA1

BSC010N04LS6ATMA1

BSC010N04LS6ATMA1 Symbol.svgDefault
BSC010N04LS6ATMA1-thumb.png

BSC010N04LS6ATMA1-thumb.png

BSC010N04LS6ATMA1-thumbThumbnail
stp

BSC010N04LS6ATMA1

BSC010N04LS6ATMA1.stp3D Model

BSC010N04LS6ATMA1

BSC010N04LS6ATMA1 thumbnail
N-Channel Power MOSFET – 40 V logic-level N-channel OptiMOS™ 6 power MOSFET optimized for high-efficiency synchronous buck converters, motor drives, battery-powered systems, and industrial power switching. Features a 40 V drain-to-source voltage (VDS), 100 A continuous drain current (TC = 25°C), 1.0 mΩ maximum RDS(on) at VGS = 10 V, and 1.4 mΩ maximum RDS(on) at VGS = 4.5 V. Includes logic-level gate drive, 67 nC typical gate charge, ±20 V gate-source voltage rating, 175°C maximum junction temperature, and 100% avalanche tested for enhanced ruggedness. Housed in an 8-pin PG-TDSON-8 (SuperSO8 5 × 6 mm) surface-mount package.

Properties

BSC010N04LS6ATMA1

Infineon

Transistor

Q

Surface Mount

parametric-v1

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