Part Audit Review

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Reading AT29C256 Pin Audit's report…
Thought for 12 sec — Investigating pin renaming
Reading schematic details for *WE, A12, A13 and 2 more.
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Reading schematic details.
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Updated designators.
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Reading schematic details.
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Steering AT29C256 Pin Mapping…
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AT29C256 Pin Mapping
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Received notification from "AT29C256 Pin Mapping" that it finished — picking the work back up.

flux

Corrected and verified all 32 terminals against the AT29C256 32J PLCC datasheet.
  • Names, pin numbers, electrical types, descriptions, grouping, and ordering now match.
  • All footprint pads map to the correct terminals with counter-clockwise numbering and correct pin-1 orientation.
  • DC pins 1/17 and NC pins 12/26 are correctly distinguished.
  • Updated Part Audit with the remediation results.
No remaining electrical or footprint-mapping mismatches were found.
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Part Audit
Scope and source
Audited the current AT29C256-90JI part metadata, 32-terminal schematic symbol, assigned PLCC32_MC_MCH footprint/model, pad geometry, and terminal properties against the attached Atmel datasheet:
Current part information

Table

FieldCurrent valueAudit
Name / MPNAT29C256-90JICorrect ordering code
Manufacturer Part NumberAT29C256-90JICorrect
Manufacturer NameEmpty in the library part propertyShould be Atmel (legacy manufacturer; now Microchip Technology)
Part TypeEmptyShould identify a parallel Flash/PEROM memory IC
DescriptionAT29C256-90JI PLCC32_MC_MCH PLCC32_MC_MCH-M PLCC32_MC_MCH-LPackage-centric and incomplete; it does not describe function/capacity/speed
Pin count32Correct for package code 32J
Designator prefixUAppropriate
Datasheet URLPreviously empty; now attachedUpdated
PackageAssigned PLCC32_MC_MCHPackage family is correct: 32-lead PLCC, package code 32J
Key datasheet specifications
  • Memory type: 5 V-only in-system programmable Flash/PEROM.
  • Organization: 256 Kbit, organized as 32,768 x 8.
  • Ordering variant: -90 = 90 ns access time; J = 32-lead PLCC; I = industrial temperature range.
  • Operating range: -40 C to +85 C.
  • Supply: 5 V +/-10% for the -90 speed grade.
  • Page size: 64 bytes.
  • Page program time: 10 ms.
  • Active current: 50 mA; CMOS standby current: 300 uA.
  • Typical endurance: greater than 10,000 write cycles.
  • Lifecycle note in the datasheet: not recommended for new designs.
  • Package: 32J PLCC, JEDEC MS-016 variation AE, 1.27 mm lead pitch. Body dimensions are approximately 12.319-12.573 mm by 14.859-15.113 mm overall.
Required 32-lead PLCC pinout

Table

PinDatasheet signalCurrent symbol signalResult
1DCNCMismatch: should be Don't Connect
2WENCCritical mismatch
3A12NCCritical mismatch
4A7A12Critical mismatch
5A6A7Critical mismatch
6A5A6Critical mismatch
7A4A5Critical mismatch
8A3A4Critical mismatch
9A2A3Critical mismatch
10A1A2Critical mismatch
11A0A1Critical mismatch
12NCA0Critical mismatch
13I/O0I/O0Correct
14I/O1I/O1Correct
15I/O2I/O2Correct
16GNDGNDCorrect
17DCI/O3Critical mismatch
18I/O3I/O4Critical mismatch
19I/O4I/O5Critical mismatch
20I/O5I/O6Critical mismatch
21I/O6I/O7Critical mismatch
22I/O7CECritical mismatch
23CEA10Critical mismatch
24A10OECritical mismatch
25OEA11Critical mismatch
26NCA9Critical mismatch
27A11A8Critical mismatch
28A9A13Critical mismatch
29A8A14Critical mismatch
30A13NCCritical mismatch
31A14WECritical mismatch
32VCCVCCCorrect
Only pins 13-16 and 32 match. The symbol appears to use an incorrect shifted mapping rather than the AT29C256 32J PLCC pinout.
Symbol and terminal-property findings
  • All 32 terminals exist, but the electrical mapping is substantially incorrect.
  • Active-low controls are visually named *CE, *OE, and *WE; the naming convention is understandable, but their pin numbers are wrong.
  • Every terminal has Pin Type: Unspecified. Recommended classifications:
    • A0-A14, CE, OE, WE: Input
    • I/O0-I/O7: Bidirectional
    • VCC: Power input
    • GND: Ground/power input
    • NC: No connect
    • DC: Don't connect / no connect, explicitly distinguished in the description
  • Pin descriptions are absent. They should describe address inputs, bidirectional data bus, active-low controls, power/ground, NC, and DC.
  • The current symbol labels four pins as NC (1, 2, 3, 30), but the datasheet has NC on 12 and 26 and DC on 1 and 17.
Footprint findings
  • The assigned footprint family is mechanically plausible for the 32J PLCC package: 32 perimeter pads, 1.27 mm pitch, approximately 0.584 x 1.600 mm pads, and body/silkscreen extents consistent with a 32-lead PLCC.
  • The 3D model and footprint assets are both named PLCC32_MC_MCH, consistent with the package class.
  • The footprint's pad signal names follow the same incorrect symbol mapping. Therefore the footprint-to-terminal association is electrically wrong even though the physical pad pattern appears appropriate.
  • The pin-1 indicator exists, but the current electrical assignment must be corrected before this part is safe to use.
Remediation status
Resolved. All 32 terminal names and pin numbers now match the datasheet, including pin 2 WE, pin 3 A12, pin 30 A13, DC pins 1 and 17, and NC pins 12 and 26. Active-low controls use the *CE, *OE, and *WE naming convention.
Electrical types, functional groups, ordering, and descriptions were added for every terminal. Address pins are Inputs, data pins are Bidirectional, control pins are Inputs, VCC is Power In, GND is Ground, and NC/DC terminals are Not Connected.
The footprint remains a 32-pad, 1.27 mm-pitch PLCC pattern. Every pad association was rebuilt or remapped to the corrected terminal, the counter-clockwise top-view sequence was verified, and the pin-1 indicator aligns with physical pad 1.
Flux internally disambiguates repeated terminal names with suffixes such as DC::P17 and NC::P26; the base terminal names remain DC and NC.

  • Scope and source

  • Current part information

  • Key datasheet specifications

  • Required 32-lead PLCC pinout

  • Symbol and terminal-property findings

  • Footprint findings

  • Remediation status