Part Verification Report


Added Pin Group and matching Section metadata for all 196 terminals using broad functional groups.
Open items:
  • Verification passed: 0 terminals missing Pin Group, 0 missing Section, and 0 mismatches between Pin Group and Section.
  • Final group counts: Ground 62, Power 36, Data Interface 32, GPIO 28, RF 16, Control Interface 13, Clock and Sync 5, Auxiliary Analog 4.
Suggested next steps:
  1. Review the schematic symbol visually for section readability.
  2. Add/adjust terminal ordering and orientation if you want the grouped symbol layout refined next.
  3. Run a final part-quality review before publishing.
Assign Terminal Order and Pin Orientation, then run a schematic/symbol review.
I’ll assign terminal order/orientation by the existing broad groups, then inspect the symbol metadata for consistency and report any remaining symbol-quality issues.
Terminal order and orientation are applied. I’m running the symbol metadata review now to catch missing or inconsistent fields.
Assigned Terminal Order and Pin Orientation for all 196 terminals: Power = order 1/Top, RF = 2/Left, Clock and Sync = 3/Left, Auxiliary Analog = 4/Left, Control Interface = 5/Left, GPIO = 6/Right, Data Interface = 7/Right, Ground = 10/Bottom.
Open items:
  • Symbol metadata review passed: 0 missing terminal orders, 0 missing orientations, consistent order/orientation per group, and Section still matches Pin Group.
  • Automated checks returned no open errors/warnings for the selected part/schematic review checks.
Suggested next steps:
  1. Visually review the regenerated symbol in the editor.
  2. Run a final full part review before publishing.
  3. If needed, refine individual within-group ordering for differential pairs and channel grouping.
Review and refine
Run final review
Refine pair ordering
Check symbol rendering
Verify footprint mapping

EXT_LO2-
Pin Number
A4
VSSA_1
Pin Number
A1
VSSA_2
Pin Number
A2
EXT_LO2+
Pin Number
A3
Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
VSSA_1
A1
Input
Ground
Ground
Bottom
10
VSSA_2
A2
Input
Ground
Ground
Bottom
10
EXT_LO2+
A3
Input
RF
RF
Left
2
EXT_LO2-
A4
Input
RF
RF
Left
2
VRFVCO2_1P3
A5
Input
Power
Power
Top
1
VRFLO2_1P0
A6
Bi-Directional
Power
Power
Top
1
MODEA
A7
Input
Control Interface
Control Interface
Left
5
RBIAS
A8
Input
Control Interface
Control Interface
Left
5
VRFLO1_1P0
A9
Bi-Directional
Power
Power
Top
1
VRFVCO1_1P3
A10
Input
Power
Power
Top
1
EXT_LO1-
A11
Input
RF
RF
Left
2
EXT_LO1+
A12
Input
RF
RF
Left
2
VSSA_3
A13
Input
Ground
Ground
Bottom
10
VSSA_4
A14
Input
Ground
Ground
Bottom
10
RX2A-
B1
Input
RF
RF
Left
2
VSSA_5
B2
Input
Ground
Ground
Bottom
10
VSSA_6
B3
Input
Ground
Ground
Bottom
10
VSSA_7
B4
Input
Ground
Ground
Bottom
10
VSSA_8
B5
Input
Ground
Ground
Bottom
10
VRFVCO2_1P0
B6
Output
Power
Power
Top
1
AUXADC_2
B7
Input
Auxiliary Analog
Auxiliary Analog
Left
4
AUXADC_1
B8
Input
Auxiliary Analog
Auxiliary Analog
Left
4
VRFVCO1_1P0
B9
Output
Power
Power
Top
1

ADRV9002BBCZ