Part Verification Report

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Added Pin Group and matching Section metadata for all 196 terminals using broad functional groups.
Open items:
  • Verification passed: 0 terminals missing Pin Group, 0 missing Section, and 0 mismatches between Pin Group and Section.
  • Final group counts: Ground 62, Power 36, Data Interface 32, GPIO 28, RF 16, Control Interface 13, Clock and Sync 5, Auxiliary Analog 4.
Suggested next steps:
  1. Review the schematic symbol visually for section readability.
  2. Add/adjust terminal ordering and orientation if you want the grouped symbol layout refined next.
  3. Run a final part-quality review before publishing.
A

adrian95

Assign Terminal Order and Pin Orientation, then run a schematic/symbol review.

flux

I’ll assign terminal order/orientation by the existing broad groups, then inspect the symbol metadata for consistency and report any remaining symbol-quality issues.

flux

Terminal order and orientation are applied. I’m running the symbol metadata review now to catch missing or inconsistent fields.

flux

Assigned Terminal Order and Pin Orientation for all 196 terminals: Power = order 1/Top, RF = 2/Left, Clock and Sync = 3/Left, Auxiliary Analog = 4/Left, Control Interface = 5/Left, GPIO = 6/Right, Data Interface = 7/Right, Ground = 10/Bottom.
Open items:
  • Symbol metadata review passed: 0 missing terminal orders, 0 missing orientations, consistent order/orientation per group, and Section still matches Pin Group.
  • Automated checks returned no open errors/warnings for the selected part/schematic review checks.
Suggested next steps:
  1. Visually review the regenerated symbol in the editor.
  2. Run a final full part review before publishing.
  3. If needed, refine individual within-group ordering for differential pairs and channel grouping.
Review and refine
Run final review
Refine pair ordering
Check symbol rendering
Verify footprint mapping
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Files

Pins

Symbol

Layout

3D View

EXT_LO2-
Pin Number
A4
VSSA_1
Pin Number
A1
VSSA_2
Pin Number
A2
EXT_LO2+
Pin Number
A3
Name
Pin #
Type
Part Type
Pin Description
Pin Group
VSSA_1
A1
Input
Terminal
Analog Ground (VSSA).
Ground
VSSA_2
A2
Input
Terminal
Analog Ground (VSSA).
Ground
EXT_LO2+
A3
Input
Terminal
Differential External LO Input 1 (LO1). If unused, connect EXT_LO2+ and EXT_LO2- to VSSA.
RF
EXT_LO2-
A4
Input
Terminal
Differential External LO Input 1 (LO1). If unused, connect EXT_LO2+ and EXT_LO2- to VSSA.
RF
VRFVCO2_1P3
A5
Input
Terminal
1.3 V internal LDO regulator input supply for RF external LO input 2 (LO2) VCO and LO generation circuitry; sensitive to supply noise.
Power
VRFLO2_1P0
A6
Bi-Directional
Terminal
1.0 V internal supply node for RF LO2 LO generation circuitry; connect with VRFVCO2_1P0 and bypass with 4.7 uF when internal LDO is used.
Power
MODEA
A7
Input
Terminal
Boot option select for DEV_CLK_IN± and DEV_CLK_OUT; connect to VSSA for differential clock receiver, or above VSSA for single-ended clock/crystal oscillator mode.
Control Interface
RBIAS
A8
Input
Terminal
Bias resistor connection; connect a 4.99 kohm 1% resistor between RBIAS and VSSA.
Control Interface
VRFLO1_1P0
A9
Bi-Directional
Terminal
1.0 V internal supply node for RF LO1 LO generation circuitry; connect with VRFVCO1_1P0 and bypass with 4.7 uF when internal LDO is used.
Power
VRFVCO1_1P3
A10
Input
Terminal
1.3 V internal LDO input supply for RF LO1 VCO and LO generation circuitry; sensitive to supply noise.
Power
EXT_LO1-
A11
Input
Terminal
Differential External LO Input 2. If used, input frequency must be 2x or higher than desired carrier frequency; if unused connect to VSSA.
RF
EXT_LO1+
A12
Input
Terminal
Differential External LO Input 2. If used, input frequency must be 2x or higher than desired carrier frequency; if unused connect to VSSA.
RF
VSSA_3
A13
Input
Terminal
Analog Ground (VSSA).
Ground
VSSA_4
A14
Input
Terminal
Analog Ground (VSSA).
Ground
RX2A-
B1
Input
Terminal
Differential Input A for Rx2. If unused, connect RX2A- and RX2A+ to VSSA.
RF
VSSA_5
B2
Input
Terminal
Analog Ground (VSSA).
Ground
VSSA_6
B3
Input
Terminal
Analog Ground (VSSA).
Ground
VSSA_7
B4
Input
Terminal
Analog Ground (VSSA).
Ground
VSSA_8
B5
Input
Terminal
Analog Ground (VSSA).
Ground
VRFVCO2_1P0
B6
Output
Terminal
1.0 V internal supply node for RF LO2 VCO circuitry; connect with VRFLO2_1P0 and bypass with 4.7 uF when internal LDO is used.
Power
AUXADC_2
B7
Input
Terminal
Input 2 to auxiliary ADC input multiplexer. If unused, do not connect.
Auxiliary Analog
AUXADC_1
B8
Input
Terminal
Input 1 to auxiliary ADC input multiplexer. If unused, do not connect.
Auxiliary Analog
VRFVCO1_1P0
B9
Output
Terminal
1.0 V internal supply node for RF LO1 VCO circuitry; connect with VRFLO1_1P0 and bypass with 4.7 uF when internal LDO is used.
Power

ADRV9002BBCZ