Pin Audit and Grouping


can you group together pins by their functions?
for example for Power, 3v3, gnd_1 gnd_2 etc
NOTE: If you group them, can you not add the same pin if you already added them in a group? You should know which pin function is common for its function.
Yes. I’ll assign each physical pin to exactly one broad functional group based on its primary datasheet function, keep Section equal to Pin Group, and organize power first/top, grounds last/bottom, with the remaining groups split left/right.
Pin grouping and datasheet-based descriptions are now applied. I’m verifying all 33 assignments and completing the metadata/package/footprint audit.
Grouped all 33 pins by their primary function with no duplicates, matching Section = Pin Group, and added datasheet-based pin descriptions. The existing official ADI datasheet URL is correct.
Audit findings
  • Correct: MPN, manufacturer, 33 pads, 32-lead 5 × 5 mm LFCSP plus EPAD, 0.50 mm pitch, and pin-to-pad numbering.
  • Key specs: 16-bit current/voltage DAC, ±33 V rails, 1.71–5.5 V logic, SPI up to 50 MHz, −40°C to +115°C.
  • Mismatches: package property says “TO” but should be LFCSP / CP-32-30; pin 31 is named VDPC instead of datasheet VDPC+; all pin electrical types remain Unspecified; EPAD description should explicitly state connection to AVSS or leave unconnected.
  • Footprint concern: the imported courtyard outline appears included in the silkscreen geometry, and the 3.7 mm exposed-pad paste aperture is not windowed.
Fix metadata issues
Correct footprint concerns
Run part review
Export verification report

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
SW+
1
Unspecified
DC-DC
DC-DC
Left
2
DC-DC Switching Output
AVDD1
2
Unspecified
Power
Power
Top
1
Positive Analog Supply
AVDD2
3
Unspecified
Power
Power
Top
1.01
Low-Voltage Analog Supply
NIC_1
4
Unspecified
Not Connected
Not Connected
Left
2.5
Not Internally Connected
AGND
5
Unspecified
Ground
Ground
Bottom
10
Analog Ground
REFGND
6
Unspecified
Ground
Ground
Bottom
10.01
Internal Reference Ground
RA
7
Unspecified
Current Setting
Current Setting
Left
3
External Current Setting Resistor
RB
8
Unspecified
Current Setting
Current Setting
Left
3.01
External Current Setting Resistor
REFIN
9
Unspecified
Reference
Reference
Left
4
External 2.5 V Reference Input
REFOUT
10
Unspecified
Reference
Reference
Left
4.01
Internal 2.5 V Reference Output
CHART
11
Unspecified
HART
HART
Left
5
AC-Coupled HART Input
VLDO
12
Unspecified
Power
Power
Top
1.02
3.3 V LDO Output
VLOGIC
13
Unspecified
Power
Power
Top
1.03
Digital Supply Input
SDO
14
Unspecified
SPI
SPI
Right
6
Serial Data Output
DGND
15
Unspecified
Ground
Ground
Bottom
10.02
Digital Ground
~RESET
16
Unspecified
Control
Control
Left
7
Active-Low Hardware Reset
~LDAC
17
Unspecified
Control
Control
Left
7.01
Active-Low DAC Load
CLKOUT
18
Unspecified
Clock
Clock
Right
7.5
Optional Divided Clock Output
SCLK
19
Unspecified
SPI
SPI
Right
6.01
Serial Clock Input
SDI
20
Unspecified
SPI
SPI
Right
6.02
Serial Data Input
~SYNC
21
Unspecified
SPI
SPI
Right
6.03
Active-Low Frame Synchronization
AD1
22
Unspecified
Control
Control
Left
7.02
Address Decode Bit 1
AD0
23
Unspecified
Control
Control
Left
7.03
Address Decode Bit 0

AD5758BCPZ-RL7