ESP32-C3 and RYLR998 Circuit Design

Thought for 7 sec

flux

目前无法继续直接修改工程：你对该工程是 view 权限，并且当前执行额度已用完，所以我不能调用编辑/布线工具。

本轮已完成的设计依据如下：

RYLR998/RYL998 LoRa 模组为 3.3 V UART 模组，VDD 典型 3.3 V，最大 3.6 V，禁止接 5 V。
UART 可与 ESP32-C3 的 3.3 V GPIO 直接连接，不需要电平转换。
按你指定的连接应为：
- GPIO21 → RYLR998 RXD
- GPIO20 ← RYLR998 TXD
- 3V3 → RYLR998 VDD
- GND → RYLR998 GND
- GPIO10 → RYLR998 NRST
RYLR998 的 VDD-GND 旁边应并联：
- 100 nF 陶瓷去耦电容，尽量贴近 VDD 引脚
- 10 uF 陶瓷/低 ESR 电容，放在 100 nF 附近
NRST 为低有效复位，建议 GPIO10 默认输出高电平；需要复位时拉低至少 100 ms。

PCB 布局/布线建议：

RYLR998 模组靠板边放置，天线区域朝外。
ESP32-C3 与 RYLR998 的天线区域都要避开铜皮、走线、过孔和器件。
3V3 到 RYLR998 VDD 走线适当加宽，建议至少 0.3 mm。
GND 使用连续地平面/地铜，保证 LoRa 发射电流回流路径短。
GPIO21/RXD、GPIO20/TXD、GPIO10/NRST 是低速数字线，正常短线布线即可，避免穿过天线区域。
电容放置顺序建议：RYLR998 VDD 引脚旁先放 100 nF，再放 10 uF。

如果要实际写入本工程，需要先 fork/复制到你有编辑权限的项目中，然后再添加 RYLR998、两个电容、上述网络连接，并完成 PCB 放置与布线。

复制可编辑项目

器件封装清单

检查现有网络

保存设计约束

GPIO21

GPIO2

GPIO20

GPIO6

GPIO7

GPIO4

GPIO0

GPIO8

GPIO10

GPIO9

GPIO1

GPIO5

GPIO3

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