Real custom Betaflight FLUXF405PROTO source and BIN/ELF/MAP have now been compiled and delivered, with integrated8MHz HSE bypass and PC0 active-low GPIO-gated self-powered CDC USB. See Firmware Build Results for artifacts, independently checked pins, tests, build/flash instructions and all unresolved gates. This replaces previous paragraphs stating no compiled target/USB integration exists; those paragraphs below are historical context.

This release is permanently BENCH-LOCKED: LOW motor pads and NULL motor backend, arming intentionally blocked, even with a detected gyro. It is real Betaflight but NOT a flight release or hardware-tested image. PB15 external gyro clock is intentionally disabled; gyro alignment CW0 is an unmeasured bench placeholder. Fixed clock overrides persisted HSE/overclock values; only CDC is allowed, MSC/composite paths are blocked/ignored until separately qualified. External regulated5V at J7pin1 mandatory; USB data-only, PA9 stays UART1TX. Current meter disabled pending calibration; ADC loading/settling and reference voltage scaling remain unqualified. Do not import stock SpeedyBee dumps, alter resources or claim proprietary-app compatibility. Existing actual-resource table below remains the inspected mapping, except PC0 is USB detection and motor/CLKIN outputs must not be enabled by this locked release.

USB DATA-ONLY, external regulated5V at J7pin1 mandatory even for programming. Add PC0 digital input USB_VBUS_PRESENT_N (no internal pull required): LOW=VBUS present, HIGH=absent. Q1 gate-isolated detector prevents USB VBUS DC injection into unpowered MCU. PA9 remains USART1TX; no other pin mapping changes. Remove PC0 from the unused-pin list below. Disable dedicated OTG_FS PA9 VBUS sensing in custom stack; initialize PC0 before USB, keep soft-disconnect asserted until LOW stable, disconnect promptly on HIGH. Do not merely disable sensing and permanently attach. Configure self-powered descriptors and no USB core-power request. HAL/version-specific bypass and PC0 callback integration must be implemented by firmware task; stock ROM DFU may not follow this custom GPIO detector, so SWD is mandatory recovery until measured. PA9 USART1TX and OTG_FS_VBUS share the physical pad. No direct5V connection was added to PA9. Q1 pin1G/pin2S/pin3D checked. Actual mapping table below otherwise unchanged; its USB-only/core-authorization/no-detector paragraphs are historical and superseded by this section.

All active-scope external interfaces are now wired. Custom prototype firmware REQUIRED; no tested binary, patch or build delivered. Do not assume stock SPEEDYBEEF405V5 compatibility. Remove absent features and change UART defaults. Source evidence and ERC limits live in interface-and-firmware-gates.

J2 order1=3V3 sense ONLY,2GND,3SWDIO,4SWCLK,5NRST,6BOOT0. Never power the LDO output from debugger3V3. PB2BOOT1 is pulled low. BOOT0 may be externally strapped to3V3 for recovery; test ROM DFU clock behavior separately.

Reference config fully read from https://github.com/betaflight/config/blob/1e3f7782bfbc/configs/SPBE/SPEEDYBEEF405V5/config.h . It names8MHz but not oscillator topology. Betaflight source https://github.com/betaflight/betaflight/blob/af0638839ac3/src/platform/STM32/startup/system_stm32f4xx.c was read through SystemInit and SetSysClock: SystemInit clears HSEBYP using0xFFFBFFFF; SetSysClock calls StartHSx(RCC_CR_HSEON,RCC_CR_HSERDY,5000) without restoring HSEBYP. Thus frequency matching is not sufficient for this active oscillator.

Chosen architecture: retainY1 active8MHz and PH1NC; custom startup must set RCC_CR_HSEBYP while HSE disabled before the HSE start, after SystemInit reset. Audit every recovery/clock-reset path. No stock binary guarantee. For unoverclockedF405 the read source computes8MHz ->pll_m4,pll_input2,pll_n168,pll_p2,pll_q7 giving168MHz core and48MHz USB. These are source-derived required values, NOT a tested implementation. Failure to become HSE/PLL ready must keep outputs inactive, not silently run flight control on a wrong timebase. Build and hardware verification remain gates.

Use distinct board/target name. Reuse only mapped active resources from source; motor TIMER_PIN_MAP selections are(2,0),(2,0),(1,0),(1,1) for M1–M4. These mapping indices are not GPIO AF numbers; datasheet AFs are shown above. Verify DMA allocation and DShot implementation for chosen Betaflight revision. Initial DShot300 unidirectional; bidirectionalDShot and cable timing not established. Set receiverUART1/GPSUART2 rather than referenceUART6/UART4; configure noninverted3.3V UART receiver protocol. No SBUS inverter supplied. UART1 is not Bluetooth/MSP by default. Disable OSD,barometer,wireless,PINIO,buzzer,LED,camera,RSSI,servo resources. NC pinsPC13/PC14/PC15/PC0/PC2/PC3/PB12/PB13/PB14/PC8/PC9/PA8/PA15/PB8/PB9 should not be initialized as stock outputs.

Start ADC sample time480cycles, rate=10ms settling when enabling channels. PC1 filter157.721Hz;PC5filter265.258Hz passive simulation. Validate real sample loading and VDDA. Firmware voltage reconstruction uses measuredVDDA, nominalVBAT=11Vadc, external sensorV=2Vadc. Then apply measured sensor slope/offset to amperes; no onboard current shunt exists. Never reuse reference current scale36. Calibrate against known supplies and current reference at multiple points. Normal sense boundVBAT25.2V;30V is a screening ceiling, not a surge rating.

GPIO CS high and motor outputs low before bus activity; retain SWD. USB-only preauthorization must stay below100mA (lowclock,flash/IMU idle); request>=250mA before168MHz logging. External5V mode permits bounded180.16mA core only, no accessory loads. There is no dedicatedUSBVBUS sense pin becausePA9 isUART1TX; inspect/configure USB device stack for no-VBUS-sense/self-powered operation and prevent attachment signaling without hostVBUS. This firmware gate is not resolved by diodeOR. Do not drive FC interface pins when FCoff; independently powered peripherals need sequencing/isolation offboard.

Read flash JEDEC and test program/erase/read. Read IMU WHO_AM_I, configure SPI and interrupt polarity explicitly. PB15CLKIN is inherited reference resource; timer frequency/mode must be validated before enabling external gyro clock. Physical alignment must follow actual future placement, not assumedCW270. Verify8MHz oscillator,clock trees,USB enumeration both orientations,DFU recovery,motor waveform and failsafe with props removed. No compiled code or flight qualification claimed.