FLUXF405PROTO is now an actually compiled, schematic-grounded Betaflight target with integrated clock and USB handling. It supersedes the previous safe-only/non-enumerating limitation below. This is a compile/host-tested BENCH-LOCKED release, NOT hardware-tested or flight-ready. No schematic/layout mutations were made by the firmware task. Full project metadata and all 69 nets were inspected; U1/U2/U3/Y1/Q1 memberships were re-inspected after implementation and still match this snapshot.

Archive contains corresponding F405 upstream source with integration changes, distinct config.h, integration.patch, shared USB decision header, host test source, mapping-check script, native-inspection-derived pin snapshot, ELF/BIN/HEX/MAP, logs, binary descriptor verification and detailed README. Pin snapshot was manually transcribed from native inspection, not an exported schematic/netlist. Prior safe-only archive URL returned HTTP403 when fetched in this task; old artifact retrieval failed, so implementation was rebuilt from pinned upstream rather than claiming to have recovered that source.

Clock: driven Y1 8MHz into PH0, PH1 NC; restore HSEBYP after SystemInit reset and before HSE enable. Fixed HSE8MHz and overclock level0 override persisted settings, yielding upstream M4/N168/P2/Q7, 168MHz core and 48MHz USB. HSE timeout spins closed before USB initialization, motor pads already LOW. Inherited PLL/SWS wait loops remain unbounded; no hardware timeout/failure-injection measurements claimed.

USB: PC0 USB_VBUS_PRESENT_N is floating input using external R36 pullup, LOW=present. PA9 remains UART1TX; upstream F4 core already disables native VBUS sensing and does not configure PA9 for USB. Core reset followed by soft-disconnect assertion precedes enabling embedded PHY. After USBD_Init readiness, shared gate runs from nominal1ms SysTick: ten LOW serviced ticks attach; HIGH resets count and disconnects on next serviced tick. DCTL update is atomic and does not call vendor3ms delay routines from ISR. Detach clears USB configured/status bookkeeping. Interrupt masking can delay ticks; this is NOT a measured detach deadline. Persisted composite selection is ignored: CDC only. MSC boot entry is disabled because its separate USB init path is not qualified. Linked CDC bytes 09024300020100c000 verify bmAttributes0xC0 self-powered and bMaxPower0, and GET_STATUS self-powered is enabled. External regulated5V at J7pin1 remains mandatory; USB never powers this board. Enumeration/reset/suspend/reconnect and absence of brief attach pulses must be measured on hardware.

Gyro: SPI1 PA5/6/7, PA4CS, PC4INT; real USE_GYRO_SPI_ICM42688P/USE_ACC_SPI_ICM42688P support. PB15 CLKIN connection is intentionally undriven; use internal sensor clock. CW0 is an explicit bench placeholder, not a measured board-axis orientation. Flash: SPI3 PB3/4/5, PC12CS, USE_FLASH_M25P16; upstream flash_m25p16.c lists JEDEC0xEF4018. Keep SWD PA13/14; no JTAG/SWO use on flash pads.

Actual motors M1PB1/M2PB0/M3PB10/M4PB11 map upstream TIM3CH4/TIM3CH3/TIM2CH3/TIM2CH4 respectively. Table candidates (mapping index,DMA option): (2,0),(2,0),(1,0),(1,1); canonical upstream dma_reqmap_mcu.c yields DMA1 streams2/7/1/6 channels5/5/3/3, avoiding the shared TIM2CH4 option0/ TIM3CH3 stream7. These are source-backed future candidates, NOT validated motor waveforms. Delivered image drives pads LOW early and forces NULL device initialization; PWM/DShot hardware init symbols are absent after LTO. Arming status deliberately reports NO_GYRO permanently even if sensor is found. CLI cannot remove source-level bench lock. Generic resource remapping and unsupported features remain available in Betaflight: do not alter resources or import stock CLI dumps on this release. Removing the lock requires a reviewed new source release.

UART1PA9/10 receiver default; UART2PA2/3 GPS default; UART3PC10/11, UART4PA0/1, UART6PC6/7; UART5PD2 RX-only. No MSP-on-UART1 default. I2C1PB6/7; ADC PC1 VBAT/PC5 current mapped, current meter source disabled pending sensor scale. No absent OSD,barometer,buzzer,LED,servo or PINIO resources are assigned. ADC loading/sample time/settling, measured voltage scale and current calibration remain gates; reference current scale36 not reused. Receiver/GPS protocols, failsafe and powered-off interface isolation not qualified.

Upstream https://github.com/betaflight/betaflight commit af0638839ac318584ac1da48cf53126e2f30f834 (2026.12.0-alpha); config baseline1e3f7782bfbc98dfde35f2086f350a4d0b3f8f6d. ARM GCC13.2.1 20231009 Ubuntu15:13.2.rel1-2; Clang18 host ASan/UBSan. Pinned checkout recipe uses make CONFIG=FLUXF405PROTO GCC_REQUIRED_VERSION=13.2.1 -j8; explicit override of upstream13.3.1 requirement. Standalone packaged source tree uses make CONFIG=FLUXF405PROTO GCC_REQUIRED_VERSION=13.2.1 AUTOHYDRATE_STAMPS= -j8 because Git submodule pointers are intentionally absent. Independently repeated archive build succeeded; its text was40B smaller because Git version metadata is absent, so archive rebuild is build-reproducible, not asserted byte-identical. Use pinned Git recipe to retain version metadata.

Final delivered link: text509886B,data6072B,bss78152B; FLASH vector392B plus FLASH1 515566B (515958B /1MiB overall49.21%); FLASH1 /992KiB50.75%. Main RAM72888/131072B55.61%, CCM11732/65536B17.90%, including2KiB heap/stack reservation; stack high-water not measured. Vector LOAD0x08000000, executable text0x08008000, configuration reservation0x08004000; BIN contains address gap and must start0x08000000. No external bootloader required. BIN SHA2565eed049c676eb8ba1fd10fdc414ba9b8e3b706a5886a728e35b150f4f5cde6d9; archive SHA2567a3f86c88008263377113ff4d7a1193e87177ab0250e9c752ea4f48b6e28827a.

Host output: PASS: active-low polarity, absent boot, ten-tick attach, saturation, bounce, detach, readiness gate; ASan/UBSan clean. Mapping check:29 pins, ten absent resources and linked ICM426xx/M25P16/readiness symbols. ELF descriptor bytes checked independently; SysTick disassembly shows PC0 read and DCTL bit updates. NULL motor backend audit confirms no motor PWM/DShot init symbols. Source-recipe smoke build succeeds. Initial descriptor preprocessor failure at usbd_cdc_core.c348 fixed/rebuilt; own binary audit caught a lock initially applied only to endpoint math, moved it to actual device init/rebuilt; descriptor audit caught missing per-target macros in vendor units, added platform.h to PHY/CDC/GET_STATUS units/rebuilt. This exposed vendor string byte/NULL warnings at usbd_req.c842/860, corrected to byte/zero. Only final hard-locked artifacts delivered. git diff --check noted inherited whitespace on two edited vendor lines (Info, nonfunctional); not a compiler error.

No hardware has been flashed, enumerated, sensor-read, motor-tested or flown. Props removed, ESC signal cables disconnected, current-limited external5V; J2pin1=3V3 SENSE ONLY, never debugger power into LDO output. SWD example after wiring verification: openocd -f interface/stlink.cfg -f target/stm32f4x.cfg -c "program fluxf405proto.elf verify reset exit". ROM DFU/USB bootloader-reset behavior unqualified; SWD recovery required. Measure clock/timebase, LOW motor reset behavior including persisted settings, gyro WHO_AM_I0x47/interrupts, flash JEDEC0xEF4018/program/erase/read, both USB orientations and powered/unpowered combinations, insertion during boot, host suspend/reset/reconnect, delayed interrupts, no backfeed. Release axis alignment, ADC calibration, receiver/failsafe, actual motor protocol/DMA waveforms and thermal/power margin only after measurement. No stock/proprietary SpeedyBee app compatibility claimed. Electrical remediation and complete product readiness are separate from completion of this firmware batch.

The remaining sections below describe the previous implementation and are superseded by the current release above wherever they say no real Betaflight/USB integration was delivered.

SAFE BRING-UP ONLY image successfully compiled and host-tested; NOT flight firmware and NOT Betaflight. No hardware testing or flight qualification. Schematic/layout untouched; only this results file and isolated firmware workspace changed. Current saved U1 and all69 nets inspected against firmware-getting-started and project-specification (80-component electrical revision).

Archive includes source, Makefile, linker/startup, README, pin-manifest.json, host tests, mapping checks, compile-tested DRAFT Betaflight target header, logs and checksum manifest. Source revision3ca37c0456e6dbd3328e60cb84c268faff5bef5a. Archive SHA25686e4ab2d48c93ab00e8433d13a62df27df222864e6590e4dd3984f677dc12291. BIN SHA2566176c0bb2ef11fafc01f125e80561baeb2d5de578ef5b00b1b97389d2d8627e6.

ARM GNU13.2.1 20231009 (Ubuntu15:13.2.rel1-2), Clang18.1.3. Bare freestanding Cortex-M4/thumb, soft-float, -Os -g3, no heap/libc, -Wall -Wextra -Werror. Dependencies: pinned Betaflight/ST CMSIS headers at af0638839ac318584ac1da48cf53126e2f30f834; config tree1e3f7782bfbc98dfde35f2086f350a4d0b3f8f6d used to research source target. Build safe image with make BF=/absolute/path/to/pinned/betaflight; host tests make host; mapping check python3 check_mapping.py. README gives clone/checkout commands and flashing cautions.

Safe image: .text1088B + .data4B = 1092 /1048576B flash (0.104%). .data4B + .bss44B + reserved4KiB stack budget = 4144 /131072B main SRAM (3.16%); CCM64KiB unused; no heap. Stack maximum not measured. Vector table at0x08000000, no bootloader offset. ELF/BIN/MAP were regenerated after correcting vendor-header include and GPIO BSRRL/BSRRH/SPI16-bit register API mismatches; final build zero compiler warnings/errors.

Upstream first attempt stopped at mk/tools_check.mk:31: requiredGCC13.3.1 versus installed13.2.1. Retried explicitly with GCC_REQUIRED_VERSION=13.2.1 and both builds succeeded. Draft BF resource-target: text536409B,data6552B,bss98628B; linker RAM92220/131072B and CCM13356/65536B. This compile evidence is NOT a valid image release: unpatched active oscillator and USB behavior fail this board's contract.

M1PB1/TIM3CH4 AF2, M2PB0/TIM3CH3 AF2, M3PB10/TIM2CH3 AF1, M4PB11/TIM2CH4 AF1 (safe image uses GPIOLOW only). Upstream timer table timer_stm32f4xx.c confirms matching alternatives, config mapping choices(2,0),(2,0),(1,0),(1,1). UART1PA9/10;UART2PA2/3;UART3PC10/11;UART4PA0/1;UART6PC6/7;UART5RXPD2. I2C1PB6/7. ADCPC1 channel11 ratio11,PC5 channel15 ratio2; not initialized or calibrated by this safe image.

IMU SPI1PA5/6/7 AF5,PA4CS,PC4INT; PB15CLKIN undriven. FlashSPI3PB3/4/5 AF6,PC12CS; keep SWDPA13/14. Safe image raises CS before bus setup and performs only WHO_AM_I(0x75) / JEDEC(0x9F) reads after nominal100ms. Mode0,prescaler256:328125Hz SPI1/164062.5Hz SPI3. diag over SWD contains magic0x53414645,clock_ok,error,ms,pc0_high,usb_requested,usb_attached,imu_who,flash_jedec,spi_error. Expected identities0x47/0xEF4018 are source-backed from accgyro_mpu.h and flash_m25p16.c; no identity has been measured.

USB data-only: external regulated4.75–5.25V J7pin1 REQUIRED. PC0 input without internal pull uses external R36; LOW=USB VBUS present. NativePA9 sensing never enabled in safe image because USB core never initialized; PA9 left undriven. Polling can be delayed during one-shot SPI waits, so timing is nominal, not a measured production detach deadline. Safe image has no USB descriptors and does NOT claim self-powered enumeration implemented.

Host output: PASS: polarity, 10ms qualification, prompt detach, readiness/clock gates, bounce, motor mask; ASan/UBSan clean. Mapping script: PASS: 28 target pin macros match inspected nets; 7 absent-resource checks; PC0 input, HSE bypass and USB stack-disabled checks. Executable inspected with size-A,objdump-h and nm: vector table64B at0x08000000, reset64B, main884B, diagnostic struct40B; final program contains no motor timer/PWM/DShot/arming functions. No runtime peripheral/register validation, external ERC/DRC or hardware tests inferred from host tests.

Warning: not ready for aircraft use, manufacturing release or stock/proprietary SpeedyBee support. Props removed and ESC signal cables disconnected for first boot. Current-limit external5V, verify rails/VCAP and oscillator before SWD. J2pin1 is3V3 sense ONLY—never power LDO output from debugger. Example after wiring verification: openocd -f interface/stlink.cfg -f target/stm32f4x.cfg -c "program safe-bringup.elf verify reset exit". ROM DFU not relied upon.

Measure8MHz drive/168MHz clock/timebase, clock-failure safe behavior, motor pins staying LOW from reset, both SPI IDs, SWD debug visibility and IMU/flash power-up timing. Then implement and test production USB GPIO-gated initial attach, immediate detach, self-powered descriptors, cable orientations and externally powered/unpowered combinations. Release gyro orientation and CLKIN only after measurements; qualify ADC loading/scales,current calibration,UART/I2C timing and powered-off interface isolation. Real Betaflight needs no-auto-arm/boot motor checks,DMA/DShot validation,failsafe and bench waveform tests. No hardware testing available; no flight-ready claim.