VCAP capacitors C5/C6: Murata 2.2µF, 16V, X7R, 0805 parts select karya; manufacturer na capacitance/ESR graphs check karya ane VCAP connections alag j rakhya. Details MLCC Qualification Review ma chhe.
Custom Betaflight: actual source sathe BIN/ELF/MAP compile karya, 8MHz oscillator bypass ane PC0-based USB detection integrate karya; mapping checks ane host tests pass thaya. Motors safety mate hard-locked OFF chhe—aa flight-ready firmware nathi. Downloads Firmware Build Results ma chhe.
Haju baki: 39 × 39mm PCB sizing, placement/routing ane hardware tests. Fresh ERC ma 10 errors haju visible chhe; connectivity inspection pramane aa USB external-source ane IMU supply-detection findings chhe, errors suppress karya nathi. Final independent review nu result reconcile karvanu baki chhe. ESC access fari fail thayu, etle tena power stages/routing ma changes nathi karya ane 55A capability verify nathi; aagal mate accessible ESC project no working link joie.
Prototype placement disposition — supersedes prior VCAP selection hold
COMPLETED focused alternative: manually downloaded/rendered manufacturer-authored Murata characteristic PDF rather than retrying native indexing. C5/C6 are now GRM21BR71C225KA12L,2.2uF16V10%X7R0805,no substitutes; Package,Manufacturer Name,Manufacturer Part Number,Datasheet URL,Allow Substitutes andRole Details changed in place (commit a8403f87). No capacitance change, rewiring or MCU mapping change. All VCAP isolation retained. Read mlcc-qualification-review for durable PDF URL/snapshot,hash,page/curve evidence and the explicit manual-versus-indexed distinction.
Page1 establishes nominal2.2uF/10%/16V/X7R0805; page2 manually inspected bias graph shows only small typical change at0–2V and blue ESR R curve=0.9VDD and VOLCORE_5V. ExistingF2/D8 protects regulatedinput; rawbattery sensing-only retained. USBalone no longer powers board.
COMPLETED: added gate-isolated VBUS presence detection Q1/R34/R35/R36;PC0 LOW=VBUSpresent. Existing PA9UART1TX and all motor/UART/I2C/ADC pins preserved. Custom firmware attach/detach still must be implemented; this electrical batch does not deliver firmware.
COMPLETED: power/ADC/sensor screening and passive analogDC/AC/transient simulation; specification/budget/firmware/bring-up/gates updated.
FAILED/BLOCKED: unconditional layout-ready or electricalrelease cannot be established until actualMLCC selection/bias/ESR, customfirmware and hardwarethermal/startup/transient/ESD tests. Detailed symbol arrangement mutation API absent; new detector has logicalnets and functionalgroup but visualwirecleanup is not completed.
UNATTEMPTED: validatedactiveLDO/MOSFETdynamicSPICE (no qualified models), PCB/layout/routing/export and firmwarebuild (outside assigned schematic scope).
Power and ratings rationale
Existing170mA logic allocation includes117mA worst listed MCU digitalrun,25mA flash,7mA oscillator,1.404mA I2C andmargin. Add0.33mA detector pullup inside margin; IMU10mA allowance plus two80uA IQ estimates =>180.16mA input allocation. MCU enabledADC analog adds1.6mA perADC and is covered by margin. External source>=250mA capability/currentlimited,4.75–5.25V only. F2 existing0.5Ahold screen and D8 existing1A40V comfortably above allocation; source remains responsible for overvoltage/transients.
U4 conservative(5.25-3.3)*0.170=0.3315W;184C/W gives61.0C rise. U5 0.0195W/3.6C rise. AP2112 recommendedVIN2.5–6V and184C/W independently confirmed. Benchambient=3.9V underworstload because allowance not guaranteedtemperaturebound.
Caps normalvoltage=1uF afterbias/temperature/tolerance; actualMPN notqualified. VCAP2.2uF lowESR requirement retained. No capacitorcurrentrating invented without rippledata.
Resistor screen: highestDC lossR287.44mW at30V,vs100mWrating;voltageacrossR2827.27V,50Vworkingminimum specified. CC at5.25V evenentirevoltage across5.1k gives5.4mW.3.3V/4.7k pullup2.32mW,3.3V/10k1.09mW,3.3V/100k0.109mW. UART1k stucklow10.89mW/3.3mA; motor100ohm short would demand33mA (GPIOunsafe and109mW), so no sustainedshort allowance: interfacesCMOS3.3V only. External poweredoff signals prohibited; ESDarrays notDC translators/isolation.
VBUS circuit evidence
USBVBUS ->R34 10k ->Q1gate;R35 100k gate->GND. Q1sourceGND,drainPC0/R36 10k->3V3. Gate-node4.090909V at4.5VVBUS,4.08341V minimum1%corner. Q1 maximumgatevoltage20V; thresholdmax2.5V at250uA; RDSon4ohmmax atVGS4.5V/25C. Gate atlowVBUS isbelowRDS characterizationvoltage, so benchvalidate PC0logiclow/temperature rather thanclaim guaranteed4ohm. Gate insulation preventsDCUSB-to-core injection; commonGND means notgalvanicisolation. USBprotectorD2 remainsVBUSreferenced.
PA9 is USART1TX andOTG_FS_VBUS. No directVBUS ties toMCU; customstack must disablePA9 sense and gateattachment fromPC0. StockROMDFU support unverified;SWD recoverycontract retained.