Board Bring-Up Plan
Current architecture and release hold
80 components/69 nets; compatible bench prototype, not a proprietary copy or flight-ready controller. External regulated4.75–5.25V only at J7pin1 through F2/D8 to CORE_5V; raw LiPo must NEVER feed that input. USB is data-only and does not power the core. All steps are planned hardware tests, not completed results. Fresh electrical audit changed no MCU mappings or circuitry.
Before assembly
Current VCAP purchase requirement: C5/C6 Murata GRM21BR71C225KA12L,2.2uF16V10%X7R0805,no substitutes. C16–C19 selected Murata4.7uF0805 retain conditional typical-derived screening. See mlcc-qualification-review for manual PDF evidence and procurement/lifecycle caveats. Schematic may proceed to prototype placement; verify changed0805 footprints and VCAP pin-adjacent short returns during layout, then qualify loaded VCAP/LDO stability on the actual board. Package/MPN requirements changed; MCU mappings and wiring did not.
Independently inspect custom header numbering and all footprints/pin1. Finish mechanical, placement, routing, thermal and DFM checks separately; no PCB qualification was performed in this electrical audit. C5/C6 concrete MPN/DC-bias/ESR evidence is now manually inspected manufacturer evidence, sufficient for prototype selection; native indexing remains pending but is not a placement blocker.
Build custom firmware with8MHz HSE bypass, correct PLL/core/48MHz USB clocks, absent-feature disables, PA9 UART1TX and PC0 active-low host VBUS detection. SWD is the recovery path; stock ROM DFU behavior is not verified.
First power — props removed
Disconnect ESCs, motors and accessories. Inspect polarity, shorts, pin1 and solder bridges. Use a current-limited bench5V supply at J7pin1 ONLY, initially100mA; this is not a USB power allowance. If current limit prevents startup, stop and investigate before raising toward the>=250mA source-capability requirement. J2pin1 is3V3 sense, not a debugger power input. J7pin3 is sensing-only, not power.
Measure J7 input, fuse/diode drops, CORE_5V, U4/U5 outputs, separate VCAP1/2 and NRST. Confirm stable3V3 rails, CORE_5V headroom under load and current consistent with180.16mA design allocation. Start atambient2.727273V nominal/2.77727V maximum1%corner; current5V->2.5V/2.525V. Cutoffs157.721/265.258Hz; monotonic<0.1% settling before10ms. Models omit ADC sampling, clamps, active supply dynamics and surges; not hardware qualification.
Measure actual ADC/VDDA at multiple DC points, use480cycle sample time initially, calibrate voltage and sensor slope/offset; do not reuse reference current scale36. Characterize ESC transients:30V ceiling is not a validated surge rating. Disconnect raw sensing whenFCoff until power-off injection is qualified or external isolation/conditioning is added.
ERC disposition and release tests
Fresh ERC retains10 Errors/0Warnings: two U2 VDD/VDDIO source-inference findings despite connected U5 VOUT on3V3_IMU, and eight J1 external-VBUS/common-ground inference findings. Checks remain visible; no dummy drivers or suppressed findings. Read electrical-completion-review for current net evidence and unresolved gates; cleanERC is not claimed.
Scope four DShot300 outputs on dummyloads/testESC first; verify boot-low, arming, failsafe, reboot and power-loss behavior. Motor series100ohm resistors/GPIO do not tolerate sustained shorts. Motor/ESCpower never passes through these signals. Only then test motors with propsremoved. BidirectionalDShot,55A ESC behavior,proprietary app support and flightreadiness are unverified.