seeedstudio / Wio-E5-LE mini Dev Board

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PCB Design for Hiker Locator

flux

1:07

Navigating conflicting instructions.

Planning PCB creation.

Planning PCB workflow.

Querying knowledge base.

Accessing knowledge base.

Clarifying project requirements.

I’ll create a PCB from your KiCad schematic for a handheld hiker-to-hiker locator. Here’s the plan I’ve prepared:
  1. Import and validate the KiCad schematic; replace any generic parts with MPN-backed library parts and clear ERC.
  2. Define board outline/mounting, choose layer count, and set design rules/stackup.
  3. Place RF/MCU/power/connectors; add ESD on exposed I/O and battery safety (reverse polarity, overcharge, charge indicators).
  4. Set power/ground strategy, run Auto-Layout, then refine critical RF/high-current routes and clear DRC.
  5. Verify part availability; finalize markings and generate Gerbers, BOM, and pick-and-place.
Click Start on the plan bar to begin. Let me know if you’d like to change anything.
Plan
Goal
  • Create a manufacturable 2-layer PCB for a handheld hiker-to-hiker locator based on the provided KiCad schematic (https://cdn.flux.ai/project/chat/attachments/SeniorDesign-76431174-ebf0-44ea-9945-46b7fe278902.kicad_sch). Emphasize 2-layer constraints, RF keepouts, and battery/ESD safety for reliable RF performance and power handling.
Implementation plan
  1. Schematic Import and Component Mapping
    1. Import the supplied KiCad schematic into the project.
    2. Map the schematic symbols to appropriate library parts with their MPNs and update the schematic with the correct links for production.
    3. Run ERC to verify and resolve any schematic errors.
  2. PCB Stackup and Configuration
    1. Configure the PCB layout for a 2-layer stackup (Top and Bottom copper layers).
    2. Define the board outline and establish mounting and mechanical constraints.
    3. Set up design rules including trace widths, clearances, and via sizes that cater to RF paths, battery power, and ESD safety.
  3. Component Placement and Critical Areas Identification
    1. Floorplan and place key components including the RF module, MCU, power management ICs, battery circuitry, charging connectors, and any ESD protection units.
    2. Mark and define RF keepout areas and ensure short, controlled RF paths.
    3. Incorporate appropriate decoupling near power inputs and critical ICs.
  4. Routing and Layout Execution
    1. Establish a ground-first strategy with a solid bottom GND pour and use stitching vias.
    2. Route critical RF paths using controlled impedance and minimal via usage.
    3. Employ Auto-Layout for initial trace routing then hand-route key traces (RF, power) to ensure compliance with design constraints.
    4. Validate the design with a complete DRC to ensure no rule violations occur.
  5. Finalization and Documentation
    1. Finalize silkscreen markings and part placements.
    2. Verify all parts and connectivity for manufacturability and system requirements.
    3. Generate Gerber files, the Bill of Materials (BOM), and the pick-and-place files.
Success criteria
  • The PCB is configured as a 2-layer board with verified mechanical and electrical design rules.
  • Critical RF paths, battery, and ESD protection circuits are compliant and appropriately placed.
  • All components from the KiCad schematic are successfully mapped, placed, and routed, with a complete DRC pass and clear manufacturing file outputs.
87 days
fluixon

fluixon

Limit the layers to 2 only.
87 days

flux

0:52

Determining plan mode.

Calling the plan tool.

Updating the plan for PCB design.

Calling the plan tool.

Got it—your PCB will be limited to a 2-layer stackup. I’ve updated the plan accordingly:
  • Configure a 2-layer stackup, then place and route with a ground-first strategy (solid bottom GND pour, stitching vias, short RF feeds).
  • Keep the rest of the flow unchanged: import KiCad schematic, map parts, place, route, DRC, then generate Gerbers/BOM/PnP.
Click Start on the plan bar to begin, or tell me if you’d like any other constraints (board size, antenna type, min trace/clearance).
Plan
Goal
  • Create a manufacturable 2-layer PCB for a handheld hiker-to-hiker locator based on the provided KiCad schematic (https://cdn.flux.ai/project/chat/attachments/SeniorDesign-76431174-ebf0-44ea-9945-46b7fe278902.kicad_sch). Emphasize 2-layer constraints, RF keepouts, and battery/ESD safety for reliable RF performance and power handling.
Implementation plan
  1. Schematic Import and Component Mapping
    1. Import the supplied KiCad schematic into the project.
    2. Map the schematic symbols to appropriate library parts with their MPNs and update the schematic with the correct links for production.
    3. Run ERC to verify and resolve any schematic errors.
  2. PCB Stackup and Configuration
    1. Configure the PCB layout for a 2-layer stackup (Top and Bottom copper layers).
    2. Define the board outline and establish mounting and mechanical constraints.
    3. Set up design rules including trace widths, clearances, and via sizes that cater to RF paths, battery power, and ESD safety.
  3. Component Placement and Critical Areas Identification
    1. Floorplan and place key components including the RF module, MCU, power management ICs, battery circuitry, charging connectors, and any ESD protection units.
    2. Mark and define RF keepout areas and ensure short, controlled RF paths.
    3. Incorporate appropriate decoupling near power inputs and critical ICs.
  4. Routing and Layout Execution
    1. Establish a ground-first strategy with a solid bottom GND pour and use stitching vias.
    2. Route critical RF paths using controlled impedance and minimal via usage.
    3. Employ Auto-Layout for initial trace routing then hand-route key traces (RF, power) to ensure compliance with design constraints.
    4. Validate the design with a complete DRC to ensure no rule violations occur.
  5. Finalization and Documentation
    1. Finalize silkscreen markings and part placements.
    2. Verify all parts and connectivity for manufacturability and system requirements.
    3. Generate Gerber files, the Bill of Materials (BOM), and the pick-and-place files.
Success criteria
  • The PCB is configured as a 2-layer board with verified mechanical and electrical design rules.
  • Critical RF paths, battery, and ESD protection circuits are compliant and appropriately placed.
  • All components from the KiCad schematic are successfully mapped, placed, and routed, with a complete DRC pass and clear manufacturing file outputs.
Set board size
Define fab rules
Antenna constraint
Power details
Flux UI question
87 days
​
Sign up to send
TX1_PC1
RST
D0_PA0
RX_PB7
3V3
TX_PB6
SWDIO
NSS_PB9
TX2_PA2
MOSI_PA10
RX2_PA3
SCL_PB15
SDA_PA15
A4_PB4
MISO_PB14
D10_PB10
D9_PA9
RX1_PC0
SCK_PB13
SWDLK
GND
A3_PB3

Reviews

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Wio-E5-LE mini Dev Board

Wio-E5-LE mini Dev Board thumbnail
The Wio-E5-LE mini Dev Board integrates and provides access to the full GPIO capabilities of the Wio-E5-LE Wireless Module (STM32WLE5JC). With support for long range protocols and global frequencies, the Wio-E5-LE mini can achieve a transmission range up to 10km in open areas. It supports EU868 and US915, making it well-suited for wireless sensor networks and other IoT devices requiring battery power, low power consumption, and long range connectivity.

Properties

U

113991156

files.seeedstudio.com/products/114993120/Wio-E5-LE%20module%20datasheet_v1.0.pdf

seeedstudio.com/Wio-E5-LE-mini-Dev-Board-STM32WLE5JC-p-5764.html

wiki.seeedstudio.com/LoRa_E5_mini/

seeed studio

Pricing & Availability

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Qty 1

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