USB Breakout Board Design

flux

0:00

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Work Completed
  • All schematic changes per steps 1–5 implemented (project description, architecture diagram, key ICs, passives, VBUS/tamper/ESD nets, ERC/DRC updates).
  • Footprints verified and BOM enriched with MPNs and manufacturer details.
  • Reviewed DRC issues and verified manufacturability items that could be completed in schematic and BOM.
Remaining Unaddressed Tasks
  • Define and assign a standard 4-layer PCB stackup (inner VBUS & GND planes).
  • Draw the board outline with slotted capture pads for USB-A pins, shield-stake holes, and mounting ears.
  • Classify nets (USB diff pairs, power, ground) and set differential impedance rules (90 Ω) and power-net trace widths.
  • Place all components on the PCB outline, including chassis-bonding features.
  • Route nets (differential pairs, power, signals) per layout rules using Auto-Layout.
  • Run manufacturability DRC checks for missing footprints, invalid layers, and floating copper in the PCB layout environment.
Success Criteria Review
  • Mechanical mating & chassis mounting: Pending (outline & placement not defined).
  • VBUS path & sensing: ✅ schematic completed.
  • One-shot tamper mechanism: ✅ schematic integration complete.
  • USB 2.0 SI (diff-pair impedance & ESD): Partial (series resistors & TVS added; impedance rules not yet applied).
  • Documentation & design-rule compliance: ✅ BOM and ERC/DRC checks in schematic done; PCB-level DRC pending.
Recommended Next Step Proceed to the “Prepare PCB Layout” phase of the Flux workflow: set up the 4-layer stackup, draw the board outline with capture pads and mounting holes, and classify nets with impedance rules. Once that’s in place, you can place components and begin routing.
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SHLD1 Shield - SHLD2 Shield
SHLD1 Shield - SHLD2 Shield
J1 VBUS - U1 VCC
GND
U2 OUT - U4 EN
J1 VBUS - U1 VCC
U2
U2
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    Ground
    A common return path for electric current. Commonly known as ground.
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  • Power Net Portal
    Power Net Portal
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Inspect

Relieved Red Power Laces

Relieved Red Power Laces
Description

Created
1 Contributor(s)
sapphirelinux

Controls

Properties

Role
Power Conversion
J2 outline width
30 px
Net Type
Power
J2 outline height
7.62mm
J2 target footprint family
ONSHORE_USB-A1VSB6
Bus Type
USB 2.0
Connector Pitch
2.5 mm
Connector Positions
4 + shield stakes
Connectivity
USB
Domain
Telecommunications
Part Type
Mechanical
Power Requirements
USB
Chassis mounting hole positions
[(-6.57mm, 0mm), (6.57mm, 0mm)]
J2 target connector family
On Shore USB-A1VSB6
J2 piggyback capture pad strategy
Adjustable slotted pad pattern to accommodate typical 4-pin right-angle through-hole USB-A receptacles with ~2.5 mm pin pitch and shield stakes at ±6.57 mm
Role Details
USB 2.0 Type-A tamper-detect interposer with integrated reverse-current protection, polyfuse, VBUS TVS, supercapacitor-based energy store, and one-shot–latched D+/D- shunt for tamper response. Implemented on a standard 4-layer stackup with inner planes for VBUS and GND/return to support USB 2.x signal integrity in a compact interposer form factor.
J2 outline depth
12 mm
System Architecture Diagram
mermaid graph TD J2["J2: USB-A Right-Angle Receptacle"] Mezz["Mezzanine PCB (Piggyback Interposer)"] CHASSIS["Chassis / Rear I/O Shield"] %% Mechanical mating J2 -->|Pin Contacts| Mezz Mezz -->|Shield Stakes| CHASSIS subgraph Power Path MP5016["U1: MP5016 Load Switch"] FUSE["F1: Polyfuse"] TVS["VBUS TVS Diode"] J2_VBUS["J2 VBUS Pad"] GND[(GND Plane)] Mezz -->|VBUS_IN| MP5016 MP5016 -->|VBUS_PROT| FUSE FUSE -->|VBUS_OUT| TVS TVS -->|Clamp to GND| GND TVS -->|VBUS_OUT| J2_VBUS end subgraph Tamper Circuit U2["U2: LTC6993 One-Shot Timer"] U3["U3: LTC3625 Supercap Charger"] U4["U4: D+/D- Shunt Switch"] Dshort["D+/D- Short Node"] J2_VBUS -->|VBUS_SENSE| U2 U3 -->|*PFO (Power-Good)| U2 U2 -->|LATCH_ENABLE| U4 U4 -->|Short D+/D-| Dshort end subgraph SI & ESD Protection Rser["R1/R2: 22Ω Series Resistors"] ESD["U5: USBLC6 ESD Array"] TP2["D+ Test Pad"], TP3["D- Test Pad"] J2 -->|D+/D-| Rser Rser -->|D+_INT / D-_INT| ESD ESD -->|Protected D+/D-| J2 ESD -->|Clamp| GND Rser --> TP2 & TP3 end %% Shield bonding SHIELD["Connector Shield"] J2 -->|SHIELD| SHIELD SHIELD -->|Bond| CHASSIS

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