Bulk Autorouting
Worked for 20 sec
I’m checking routing prerequisites first; the bulk autoroute backend isn’t exposed in my available project tools, so I’ll verify whether I can still proceed with available routing operations or need to hand this back to the UI action.
Worked for 1 min 1 sec
I couldn’t run the bulk autorouter from my available project tools; only targeted pad-to-pad routing is exposed here. I did re-run DRC: the board still has 173 airwire errors and no returned copper-overlap/dangling/under-connected-via errors; the high-current nets to manually review after UI autoroute are 24V_RAW, 24V_BUS, 5V_BULK, 15V_PRE/15V_LASER, 12V_POS_RAW, 12V_NEG_RAW, 15V_ISO_POS/NEG, U2_SW, U5_SW, and U7_SW.
Open items:
- Bulk autoroute still needs to be launched from the Flux UI.
- After autoroute, those power and switch-node nets should be widened/replaced with pours where current or ripple is significant.
Suggested next steps:
- Run bulk autoroute in the PCB UI.
- Ask me to re-run DRC immediately after it completes.
- Ask me to inspect/widen the high-current nets manually after the autoroute result exists.
Route, review, document
Prepare cleanup checklist
Review power net widths
Check routing constraints
Document manual cleanup
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Ask about this doc
Schematic Capture Notes
Project: FLIPR Power Distribution Board
Status: Draft schematic capture completed for first-pass review
Review result: ERC checks for floating pins, no-connects, single-pin nets, power pins, undriven nets, pin-to-pin issues, shorted components, decoupling, and capacitor voltage ratings returned no ERROR/WARNING items at 2026-07-11T19:10:23Z.
Status: Draft schematic capture completed for first-pass review
Review result: ERC checks for floating pins, no-connects, single-pin nets, power pins, undriven nets, pin-to-pin issues, shorted components, decoupling, and capacitor voltage ratings returned no ERROR/WARNING items at 2026-07-11T19:10:23Z.
Captured Architecture
- 24 V input through TPS26630RGE industrial eFuse to protected 24V_BUS.
- 5V_BULK generated by LT8645S Silent Switcher buck and protected by TPS25940 branch eFuse for LabJack output.
- 5V_ANA generated by LMR33630 6 V pre-buck, TPS7A4701 low-noise 5 V LDO, and TPS25940 analog-output eFuse.
- +15V_LASER generated by LM5013 pre-buck to about 15.7 V and LT1963A LDO to 15 V.
- +/-12V_DET generated by isolated +/-15 V module followed by LT3045 and LT3094 low-noise LDOs.
- Output ferrites, connector-side bulk/HF capacitors, and damping RC branches were included on the major outputs.
Datasheet-Derived Support Values Used
Table
| Block | Key values captured |
|---|---|
| TPS26630 input eFuse | RILIM 3.32k for about 5.42 A; UVLO/OVP divider 887k / 29.4k / 34k for about 18 V UVLO and 33 V OVP; dVdT 47 nF for about 23 ms slew at 24 V |
| LT8645S 5 V buck | 500 kHz reference values: RT 88.7k, FB 1M / 243k, L 4.7 uH, 2x47 uF output, 10 nF soft-start, 2.2 pF feed-forward |
| TPS25940 LabJack eFuse | RILIM 20k for about 4.45 A; dVdT 4.7 nF for about 2 ms ramp |
| TPS25940 analog eFuse | RILIM 88.7k for about 1.0 A; dVdT 4.7 nF |
| LMR33630 6 V pre-buck | FB 100k / 20k for 6 V; 10 uH inductor; 4x22 uF output; 100 nF bootstrap; 1 uF VCC cap |
| TPS7A4701 5 V LDO | ANY-OUT mode using 0.4 V and 3.2 V pins grounded; 10 uF input, 47 uF output, 1 uF NR cap |
| LM5013 15.7 V buck | RON 130k for about 300 kHz; FB 604k / 49.9k; 22 uH inductor; 2.2 nF bootstrap; SS56 catch diode; Type-3 ripple network 604k / 3.3 nF / 56 pF |
| LT1963A 15 V LDO | Adjust divider 13.7k / 1.21k; 10 uF input; 10 uF output plus 47 uF bulk/damping |
| LT3045 +12 V LDO | RSET 121k for +12 V; 4.7 uF SET cap; 10 uF input/output caps |
| LT3094 -12 V LDO | RSET 121k for -12 V; 4.7 uF SET cap; 10 uF input/output caps; VIOC tied to GND for standalone use |
Filter Damping Notes
- Each major output includes a ferrite bead plus connector-side bulk and HF capacitance.
- Damping RC branches were added to avoid a high-Q ferrite/ceramic-cap resonance:
- 5V_LAB: 0.47 ohm + 10 uF
- 5V_ANA: 0.47 ohm + 10 uF at connector branch, plus local 1 ohm + 10 uF branch on the analog LDO output
- +15V_LASER: 1 ohm + 10 uF
- These are first-pass damping values. Final values should be verified with impedance/ringing simulation or bench load-step testing once final ferrite impedance curves and cable/load capacitance are known.
Open Items Before Layout
- Replace provisional output connectors with exact Thorlabs-compatible Mini-XLR / LDS12B-style mating connectors once part numbers and pinouts are confirmed.
- Confirm FLIPR analog-board 5 V current. Current schematic limits the low-noise 5V_ANA output to about 1 A.
- Confirm whether the PDA45 detector really needs 500 mA continuous per rail. If yes with margin, parallel LT3045/LT3094 devices or use higher-current LDO alternatives.
- Verify LT3094 EN/UV and VIOC tie-offs against final ADI application circuit before manufacturing release.
- Validate LT8645S, LMR33630, and LM5013 compensation/stability with final magnetics, capacitors, and layout parasitics.
- Verify ferrite bead impedance/current derating curves, especially MFBM1V2012-000-R where library search did not confirm useful 100 MHz impedance.
- Assign final PCB footprints/packages to generic passives and confirm thermal pad/via requirements for power ICs.
- Run physical-constraint setup next: 4-layer stackup, current-rated trace/pour rules, thermal copper requirements, and connector placement constraints.
Captured Architecture
Datasheet-Derived Support Values Used
Filter Damping Notes
Open Items Before Layout
