Bulk Autorouting

flux

DRC is currently failing only on Airwires: 173 errors — those are unrouted connections, not a blocker to autorouting; they are what the autorouter should consume. I did not see blocking DRC categories like missing footprints, invalid layers, components outside board, body overlaps, pad-access clearance issues, dangling traces, or copper overlaps in the returned checks.
Open items:
  • Bulk autorouting should be possible from a DRC standpoint.
  • This is a power distribution board, so high-current rails may still need manual trace/polygon sizing after autoroute.
  • The active user rule set is Auto-Layout: Universal Keepout, enabled.
Suggested next steps:
  1. Run bulk autoroute on the 173 airwires.
  2. Re-run DRC afterward for shorts/overlaps/under-connected vias.
  3. Manually review and widen high-current VIN/OUT/SW paths and add copper pours where needed.
S

sagea

flux

I’ll bulk autoroute the current airwires, re-run DRC, then inspect the routed power paths for any high-current segments that should be manually widened or converted to pours.

flux

I’m checking routing prerequisites first; the bulk autoroute backend isn’t exposed in my available project tools, so I’ll verify whether I can still proceed with available routing operations or need to hand this back to the UI action.

flux

I couldn’t run the bulk autorouter from my available project tools; only targeted pad-to-pad routing is exposed here. I did re-run DRC: the board still has 173 airwire errors and no returned copper-overlap/dangling/under-connected-via errors; the high-current nets to manually review after UI autoroute are 24V_RAW, 24V_BUS, 5V_BULK, 15V_PRE/15V_LASER, 12V_POS_RAW, 12V_NEG_RAW, 15V_ISO_POS/NEG, U2_SW, U5_SW, and U7_SW.
Open items:
  • Bulk autoroute still needs to be launched from the Flux UI.
  • After autoroute, those power and switch-node nets should be widened/replaced with pours where current or ripple is significant.
Suggested next steps:
  1. Run bulk autoroute in the PCB UI.
  2. Ask me to re-run DRC immediately after it completes.
  3. Ask me to inspect/widen the high-current nets manually after the autoroute result exists.
Route, review, document
Prepare cleanup checklist
Review power net widths
Check routing constraints
Document manual cleanup
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Layout Readiness Checklist
Project: FLIPR Power Distribution Board
Purpose: Execution checklist for the next layout pass: 4-layer stackup, footprint assignment, connector replacement, and constrained PCB placement.
Status: Draft checklist to use before enabling routing or manufacturing export.
1. Preconditions
  • Confirm schematic is the intended first-pass baseline.
  • Re-run ERC after any connector replacement or package-driven symbol change.
  • Confirm no remaining placeholder net names or provisional components in the power path.
  • Confirm target board envelope or enclosure mounting constraints.
  • Confirm assembly preference, copper weight preference, and hand-soldering constraints if any.
2. Stackup and Board Foundation
2.1 Required Stackup
  • Configure a Standard 4 Layer PCB stackup.
  • Assign layers as:
    • L1 Top: components, short high-current routes, switching hot-loop routing.
    • L2 Inner 1: continuous solid GND plane.
    • L3 Inner 2: power distribution planes/pours.
    • L4 Bottom: secondary signal/power routing only where needed.
  • Preserve L2 as an unbroken ground reference; avoid splits under switching loops, eFuse sense paths, and output-filter return paths.
  • Prefer copper pours/planes instead of narrow traces for 24V_BUS, 5V_BULK, 5V_LAB, 5V_ANA, +15V_LASER, +12V_DET, and -12V_DET.
  • Define one controlled power-ground / analog-ground tie strategy; do not create accidental return-current bottlenecks.
2.2 Board Size and Mechanical Setup
  • Read layout density/component area before board sizing.
  • Pick board dimensions from actual component area plus routing/thermal margin, not from the current default placement bounding box.
  • Include clearance around high-power regulators for copper spreading and heat-sink access.
  • Include mounting holes compatible with the chosen enclosure or optical-breadboard hardware.
  • Reserve connector-edge regions for internal cable routing.
  • Leave service access to input protection and output connectors.
2.3 Initial Layout Rules to Set
  • Set clearance rules suitable for 24 V industrial power distribution with margin.
  • Set current-rated width/pour expectations:
    • 24 V input path: at least 5 A design intent.
    • 5V_BULK / 5V_LAB path: up to about 4 A.
    • +15V_LASER path: at least 1.5 A.
    • +12V_DET and -12V_DET paths: at least 0.5 A each.
  • Use thermal relief intentionally: strong thermal connections for high-current power pins; manufacturable reliefs for connectors/passives where needed.
  • Add via-stitching expectations around switching converters and output filters.
3. Footprint Assignment Checklist
3.1 Power ICs and Modules
  • Confirm exact package/land pattern for TPS26630RGE input eFuse.
  • Confirm exact package/land pattern and exposed-pad requirements for LT8645S 5 V bulk buck.
  • Confirm exact package/land pattern for LMR33630 6 V pre-buck.
  • Confirm exact package/land pattern for TPS7A4701 5 V analog LDO.
  • Confirm exact package/land pattern for LM5013 +15 V pre-buck.
  • Confirm exact package/land pattern for LT1963A +15 V LDO.
  • Confirm exact package/land pattern for isolated ±15 V module.
  • Confirm exact package/land pattern for LT3045 +12 V LDO.
  • Confirm exact package/land pattern for LT3094 -12 V LDO.
  • Confirm exact package/land pattern for TPS25940 LabJack and analog output eFuses.
  • Add thermal vias under all exposed-pad regulators/eFuses where the datasheet recommends them.
3.2 Magnetics, Power Diodes, and Protection
  • Assign inductor footprints with current saturation margin and adequate pad copper:
    • 4.7 uH for LT8645S.
    • 10 uH for LMR33630.
    • 22 uH for LM5013.
  • Confirm SS56 catch diode footprint and thermal copper for LM5013.
  • Confirm SMBJ24A or final TVS footprint, standoff voltage, and surge-current rating.
  • Confirm eFuse current-set resistor footprints are stable, low-leakage, and placed close to the IC pins.
  • Confirm dVdT/soft-start capacitor footprints and voltage ratings.
3.3 Generic Passives
  • Assign packages for all generic resistors.
    • Feedback/setpoint resistors: prefer 0603 or 0805 with 0.1% where rail accuracy matters.
    • Current-limit and UVLO/OVP dividers: use appropriate voltage rating and tolerance.
    • Damping resistors: verify power dissipation and use larger package if required.
  • Assign packages for all generic capacitors.
    • High-frequency bypass: 0402/0603 only where assembly allows; otherwise 0603/0805.
    • Regulator input/output MLCCs: verify voltage derating and effective capacitance.
    • Bulk/damping capacitors: use packages with ripple-current and voltage margin.
    • Negative-rail capacitors: confirm polarity and voltage rating.
  • Assign packages for ferrite beads.
    • Verify DC current rating and impedance near 100 MHz for each rail.
    • Confirm DCR is acceptable at rail current.
    • Re-check MFBM1V2012-000-R or replace if impedance data remains unverified.
  • Assign testpoint footprints for all generated rails and important control/fault signals.
4. Connector Replacement Checklist
4.1 Input Connector J1
  • Choose exact connector type: locking barrel, threaded circular DIN, or another rugged 24 V connector.
  • Confirm rating above required input current with derating.
  • Confirm polarity/pinout and mechanical orientation.
  • Confirm footprint, panel/enclosure clearance, and cable bend radius.
  • Place near the input protection/eFuse block to keep the unprotected 24 V path short.
4.2 Laser Output J2
  • Confirm exact Thorlabs GSL49A / DS15-compatible mating connector and cable interface.
  • Confirm whether the board-side part should be Mini-XLR female, circular connector, or a harness connector.
  • Confirm pinout for +15 V, GND, and any shield/chassis connection.
  • Confirm current rating at 1.5 A continuous with margin.
  • Replace provisional connector only after the exact footprint and pin numbering are known.
  • Add clear silkscreen polarity and rail labels.
4.3 SiPM Detector Output J3
  • Confirm exact Thorlabs PDA45 / LDS12B-style mating connector.
  • Confirm +12 V, -12 V, GND, and shield/pin numbering.
  • Confirm per-pin current rating and creepage/clearance for ±12 V.
  • Replace provisional connector only after exact footprint/pin numbering is verified.
  • Keep +12 V and -12 V output filters symmetric and close to the connector.
4.4 LabJack +5 V Output J4
  • Choose final power interface: screw terminal, internal USB power-only connection, or board-to-board harness.
  • Confirm LabJack T7 Pro power input method and maximum expected current.
  • Confirm connector current rating for the full 5V_BULK / 5V_LAB load.
  • Place near the high-current 5 V eFuse/filter block.
  • Add polarity and fuse-limit labels on silkscreen.
4.5 FLIPR Analog +5 V Output J5
  • Choose final locking Molex KK / MicroFit / similar keyed connector.
  • Confirm 5V_ANA current target; current schematic limits this branch to about 1 A.
  • Confirm whether separate analog ground return pins are needed.
  • Place away from switching nodes and high-current LabJack return currents.
  • Add polarity and low-noise rail labels on silkscreen.
5. Placement Constraint Checklist
5.1 Global Placement Strategy
  • Place J1 input at one board edge, with TPS26630 input eFuse, TVS, input bulk capacitance, and protection parts immediately behind it.
  • Place output connectors on accessible edges grouped by subsystem:
    • J2 +15 V laser near the +15 V regulator/filter block.
    • J3 ±12 V detector near the isolated module and detector LDO/filter block.
    • J4 high-current 5 V LabJack near the 5V_BULK buck/eFuse/filter block.
    • J5 low-noise 5V_ANA away from switching converters and near analog-filter output.
  • Keep switching converter blocks physically separated from sensitive analog outputs.
  • Arrange power flow left-to-right or input-to-output with minimal crossing.
  • Keep testpoints accessible along the top side where possible.
5.2 Switching Converter Constraints
For each buck/converter block:
  • Place input bypass capacitors within a few millimeters of VIN/GND pins.
  • Place bootstrap capacitor next to BOOT/SW pins.
  • Keep switch node copper compact and away from connectors/output harnesses.
  • Place inductor immediately at the switch node, then output capacitors close to the inductor/output return.
  • Route feedback divider away from switch node and sense after the output capacitor/filter point required by the datasheet.
  • Provide a quiet return for feedback/setpoint components.
  • Stitch ground vias near input/output capacitors.
5.3 LDO Constraints
  • Place LDO input capacitors close to IN/GND pins.
  • Place LDO output capacitors close to OUT/GND pins.
  • Place SET/NR/ADJ capacitors and resistors close to their pins and away from high-current traces.
  • Provide large copper connected to thermal pad/output plane where datasheet allows.
  • Keep LDO output filter immediately downstream of the LDO and before the connector branch.
5.4 eFuse and Protection Constraints
  • Keep input eFuse VIN/VOUT current path wide and direct.
  • Place current-limit, UVLO/OVP, and dVdT parts close to the eFuse pins.
  • Place TVS diode close to J1 and route to ground with a short, low-inductance return.
  • Place output eFuses between regulator/filter source and connector branch as intended by the schematic.
  • Keep fault/power-good/testpoint access visible and away from high-current copper where possible.
5.5 Output Filter Constraints
  • Place ferrite bead in series with each outgoing rail close to the connector-side filter boundary.
  • Place connector-side bulk, 0.1 uF, and 0.01 uF capacitors close to the connector pins.
  • Place damping RC branches close to the filtered output node they damp.
  • Keep filter ground returns tied into the continuous plane through short via paths.
  • Preserve physical separation between noisy pre-filter and quiet post-filter copper.
5.6 Thermal Constraints
  • Give LT8645S, LMR33630, LM5013, TPS7A4701, LT1963A, LT3045, LT3094, TPS26630, and TPS25940 parts copper spreading regions.
  • Add thermal-via arrays under exposed pads according to datasheets.
  • Avoid crowding tall electrolytic/bulk capacitors against heat-critical ICs.
  • Keep hot regulators away from thermally sensitive connectors/cables where possible.
  • Re-run thermal estimate after placement using actual copper area and package choices.
6. Post-Placement Review Checklist
  • Run DRC/placement review immediately after constrained placement.
  • Verify all components are inside the board outline and not overlapping.
  • Verify connector orientation and pin-1 markings against mating cables.
  • Verify high-current path lengths are short and wide.
  • Verify switch nodes are compact and not routed under/near output connectors.
  • Verify L2 ground plane can remain continuous under critical areas.
  • Verify analog output connector and 5V_ANA filter are physically isolated from switching hot loops.
  • Verify all decoupling capacitors are close enough to their target pins.
  • Verify thermal pads have feasible via and copper escape regions.
  • Update schematic/layout notes with any footprint substitutions or connector decisions.
7. Open Decisions Before Mutation
  • Exact board size or enclosure envelope.
  • Final connector part numbers for J1–J5.
  • Exact Thorlabs-compatible connector pinouts for J2 and J3.
  • Whether +12 V and -12 V rails require more than 500 mA continuous margin.
  • Final 5V_ANA current target and whether 1 A branch limit is acceptable.
  • Preferred passive package sizes and assembler constraints.
  • Preferred copper weight, especially for 5 V 4 A and thermal spreading.
8. Exit Criteria for Layout Setup Phase
  • Board has a confirmed 4-layer stackup.
  • Board size and mounting pattern are set.
  • All components have manufacturable footprints.
  • Provisional connectors are replaced or explicitly documented as placeholders.
  • Placement constraints are captured for converters, LDOs, eFuses, connectors, filters, testpoints, and thermal-critical parts.
  • Post-placement DRC/review has no blocking errors.
  • Remaining risks are documented before routing starts.

  • 1. Preconditions

  • 2. Stackup and Board Foundation

  • 2.1 Required Stackup

  • 2.2 Board Size and Mechanical Setup

  • 2.3 Initial Layout Rules to Set

  • 3. Footprint Assignment Checklist

  • 3.1 Power ICs and Modules

  • 3.2 Magnetics, Power Diodes, and Protection

  • 3.3 Generic Passives

  • 4. Connector Replacement Checklist

  • 4.1 Input Connector J1

  • 4.2 Laser Output J2

  • 4.3 SiPM Detector Output J3

  • 4.4 LabJack +5 V Output J4

  • 4.5 FLIPR Analog +5 V Output J5

  • 5. Placement Constraint Checklist

  • 5.1 Global Placement Strategy

  • 5.2 Switching Converter Constraints

  • 5.3 LDO Constraints

  • 5.4 eFuse and Protection Constraints

  • 5.5 Output Filter Constraints

  • 5.6 Thermal Constraints

  • 6. Post-Placement Review Checklist

  • 7. Open Decisions Before Mutation

  • 8. Exit Criteria for Layout Setup Phase