Memoria para Operaciones Aritméticas

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Trabajo realizado
  • Actualicé la descripción del proyecto para documentar la integración del registro de 4 bits SN74LS173 y el multiplexor 4-bit SN74LS157, incluyendo hashtags #4bitMemory, #Modulo16 y #Debounce.
Tareas pendientes
  1. Añadir propiedad “System Architecture” con el diagrama de flujo en mermaid.
  2. Incorporar los componentes:
    • Registro D de 4 bits SN74LS173.
    • Multiplexor 4-bit 2:1 SN74LS157.
    • Tres interruptores SPST para STORE, CLR y SELECT.
  3. Añadir componentes de soporte:
    • Cuatro condensadores de desacoplo de 0.1 µF.
    • Tres resistencias de pull-down de 10 kΩ.
    • Tres circuitos RC (1 kΩ + 100 nF) para anti-rebote en STORE, CLR y SELECT.
  4. Realizar todas las conexiones entre sumador/restador, registro, multiplexor y controles.
  5. Completar la revisión de esquemático (ERC/DRC).
  6. Verificación final de STORE, CLR y SELECT.
Revisión de criterios de éxito
  • ❌ Registro de 4 bits almacena y borra (CLR) correctamente.
  • ❌ Multiplexor selecciona entre operando externo y memorizado.
  • ❌ Señales STORE, CLR y SELECT con anti-rebote.
  • ❌ Sistema integrado funciona en rango 0–15 y muestra en displays.
Siguiente paso recomendado Agregar la propiedad de proyecto “System Architecture” y establecer su valor en el diagrama de flujo mermaid que muestra la interconexión de 74LS283, SN74LS173 y SN74LS157 con STORE, CLR y SELECT.
53 days

Started implementing a plan

# Goal

- Modify the existing SUMADOR Y RESTADOR project to be fully compatible with Proteus 8.0. This includes aligning the logic family to 5V TTL, adding a 4‑bit result memory (storing values 0–15) with STORE/CLR functionality, integrating a 4‑bit 2:1 MUX for operand selection via a SELECT signal, and implementing clean debounced controls.

# Implementation plan

1. **Standardize and Verify Power and Logic

1. Set all active components (e.g., 74LS283, 74LS86, 74LS48) to operate at a consistent +5V TTL level.

2. Confirm VCC and GND rails are explicitly defined and uniformly connected in the schematic.

2. **Proteus 8.0 Compatibility and 7‑Segment Displays

1. Ensure the BCD drivers and 7‑segment displays (common‑anode) are correctly paired and the 220Ω resistors remain on each segment.

2. Adjust any legacy configuration so that Proteus recognizes and simulates the parts accurately.

3. **Integrate the 4‑Bit Memory and 2:1 MUX

1. Add a 4‑bit D register (e.g., LS173) configured for 5V TTL with asynchronous clear for storing the result from the 74LS283 adder.

2. Insert a 4‑bit 2:1 MUX (e.g., LS157) to select between the adder output (SUM[3:0]) and the stored memory (MEM[3:0]).

3. Connect the adder outputs to the D register inputs and wire the register outputs into one input branch of the MUX. Wire the adder output directly to the other MUX branch.

4. Label nets as SUM[3:0] (adder outputs) and MEM[3:0] (memory outputs), with a control net SELECT to choose the MUX input.

4. **Implement Debounced Controls

1. Add hardware debouncing circuits (using RC networks with Schmitt trigger buffers or flip‑flop-based debouncers) for the STORE, CLR, and SELECT signals.

2. Wire the debounced STORE control to trigger the D register’s clock, and wire the CLR to asynchronously reset the memory.

3. Ensure the SELECT control is clean and directly controls the MUX selection input.

5. **Finalize Net Naming and Verification

1. Rename all relevant nets to follow standard conventions: A[3:0], B[3:0], SUM[3:0], MEM[3:0], CIN, and COUT.

2. Run ERC/DRC checks in Proteus to verify that all components (including the new memory and debouncing circuits) are correctly connected.

3. Prepare a Proteus wiring map to guide the user for direct download and use.

# Success criteria

- The project is fully compatible with Proteus 8.0 with standardized 5V TTL components.

- The added 4‑bit memory correctly stores values (0–15) from the adder, and the STORE/CLR functions operate as expected.

- The 4‑bit 2:1 MUX seamlessly selects between the adder output and stored memory based on the debounced SELECT signal.

- All nets are properly named (A[3:0], B[3:0], SUM[3:0], MEM[3:0], CIN, COUT) and verified by ERC/DRC.

- Clean, debounced control signals are incorporated with reliable STORE, CLR, and SELECT functionality.

52 days

flux

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I haven’t been able to make any changes because execution stopped prematurely (insufficient credits).
Work done
  • None of the implementation plan steps have been executed.
Success criteria
  • ❌ Proteus compatibility not achieved
  • ❌ 5 V TTL alignment not applied
  • ❌ 4-bit memory and MUX integration not added
  • ❌ Debounced controls not implemented
  • ❌ Net renaming and ERC/DRC verification not performed
Next recommended step Proceed with step 1 of your plan: define and connect explicit +5 V and GND rails, and set all IC power pins (74LS283, 74LS86, 74LS48, etc.) to +5 V TTL.
52 days

Ready.

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R9
Resistance
220 Ω
74LS86
74LS283
SW1
S1
74LS48
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SUMADOR Y RESTADOR

SUMADOR Y RESTADOR
Description

Created
Last updated by sagc
1 Contributor(s)
sagc

Controls

Properties

Role Details
4-bit sum/subtract unit with operand multiplexer, result register, and debounced modulo-16 operation using 74LS283 adder, 74LS173 register, 74LS157 multiplexer, and 74LS86 for arithmetic control and debouncing.
Integrated Circuit Type
Logic
Logic Function
Multi Function
Part Type
Integrated Circuit
Operating Voltage
5 V
Domain
Scientific
System Architecture
```mermaid flowchart TD LS283_O["74LS283 Sum/Diff Outputs\nA1-A4"] --> REG_D["SN74LS173 Data Inputs\nD0-D3"] REG_Q["SN74LS173 Outputs\nQ0-Q3"] --> MUX_IN["SN74LS157 Data Inputs\nD0-D3"] EXT_OP["External Operand Bus"] --> MUX_IN SELECT["SELECT"] --> MUX_SEL["SN74LS157 Select Pin"] MUX_IN --> MUX_Y["SN74LS157 Outputs\nY0-Y3"] MUX_Y --> LS283_A["74LS283 Inputs\nA1-A4"] STORE["STORE"] --> LOAD["SN74LS173 LOAD Pin"] CLR["CLR"] --> CLEAR["SN74LS173 CLEAR Pin"] ```
Role
Control Unit

Availability & Pricing

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