USB C WiFi BLE Sensor Node
Worked for 7 mins 17 sec
Created 4 project docs
Design Notes — USB-C WiFi BLE Environmental Node
Input: USB-C receptacle J1, 5 V sink-only, USB 2.0 D+/D- routed to ESP32-C3 native USB Serial/JTAG. USB-C configuration: R1/R2 = 5.1 kΩ Rd f...
View docFirmware Starter — ESP32-C3-WROOM-02-N4
MCU/module: ESP32-C3-WROOM-02-N4 Framework: Arduino on PlatformIO
View docBoard Bring-Up Plan — USB-C WiFi BLE Environmental Node
Equipment: current-limited 5 V USB supply or USB power meter, multimeter, oscilloscope, USB-C cable, ESD-safe workstation, PlatformIO firmwa...
View docTechnical Construction File — USB-C WiFi BLE Environmental Node
Draft, schematic-stage. FCC Part 15 intentional radiator integration using pre-certified module conditions.
View docImplemented the schematic for the USB-C powered Wi‑Fi/BLE temperature/humidity node and created the supporting project files:
Open items:
- PCB layout has not been started yet; airwires are expected until placement/routing.
- Generic passives/testpoints still need production MPN assignment before manufacturing export.
- Layout must enforce ESP32 antenna keepout and keep the SHT40 away from heat sources.
Suggested next steps:
- Set board size/stackup and antenna/sensor placement constraints.
- Place components with the ESP32 antenna at the board edge.
- Route USB, buck power, and I2C nets.
- Assign production MPNs for generic passives and test pads.
Create layout constraints
Assign passive MPNs
Run schematic review
Start PCB placement
Prepare layout intent
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Board Bring-Up Plan — USB-C WiFi BLE Environmental Node
Prerequisites
Equipment: current-limited 5 V USB supply or USB power meter, multimeter, oscilloscope, USB-C cable, ESD-safe workstation, PlatformIO firmware image.
Safety/current-limit start point: begin at 5.0 V with a 300 mA current limit if using a bench USB source. Increase to 750 mA only after confirming no shorts.
1. Visual Inspection
- Verify J1 USB-C solder joints and shell stakes.
- Verify U1 TPS259530DSGR WSON orientation and exposed pad soldering.
- Verify U2 TPS62821DLCR orientation, L1 placement, and polarity-free ceramic capacitors.
- Verify D2 pin 1 on
VBUS_RAW, pin 2 to GND. - Verify SHT40 U4 is clean, uncovered, and not contaminated by flux residue.
- Verify ESP32 antenna area is not obstructed by metal, copper, or components in layout.
2. Power Rail Verification
Table
| Rail | Source | Expected Voltage | Measure At | Current Limit | Pass Criteria |
|---|---|---|---|---|---|
VBUS_RAW | USB-C J1 | 4.75-5.25 V | TP1 | source-limited | Stable 5 V, no heating |
VBUS_PROT | U1 eFuse OUT | 4.75-5.25 V after startup | TP2 | ~0.76 A eFuse limit | Follows VBUS after UVLO; no FLT asserted |
3V3 | U2 buck | 3.20-3.40 V | TP3 | 1 A regulator capability | Stable, low ripple, ESP32 boots |
| GND | Board ground | 0 V reference | TP4 | n/a | Continuity to USB shell/GND |
Procedure:
- With no power, measure resistance from
VBUS_RAW,VBUS_PROT, and3V3to GND. - Apply 5 V through a current-limited source.
- Confirm
VBUS_RAWat TP1. - Confirm U1 releases
VBUS_PROTat TP2 after UVLO threshold is satisfied. - Confirm U2 generates 3.3 V at TP3.
- Check U1 FLT net and U2 PG net via firmware or probe if available.
3. Critical Signal Verification
Table
| Signal | Net | Expected State | Measure At | Notes |
|---|---|---|---|---|
| ESP32 enable | ESP_EN | High ~3.3 V after RC delay | TP10 | SW2 pulls low to reset |
| BOOT | ESP_BOOT | High ~3.3 V normally | TP9 | SW1 pulls low for download mode |
| GPIO2 strap | ESP_GPIO2_STRAP | High ~3.3 V | U3 IO2/R11 | Required normal SPI boot recommendation |
| Buck PG | BUCK_PGOOD | High when 3V3 valid | U3 IO5/R8 | Open-drain pull-up |
| eFuse FLT | EFUSE_FLT | High when no fault | U3 IO4/R15 | Open-drain pull-up |
| USB D+/D− | USB_DP/USB_DN | USB FS activity during enumeration | J1/D1/U3 | Keep away from buck SW node in layout |
| I2C | I2C_SDA/I2C_SCL | Pull high to 3.3 V idle | TP5/TP6 | SHT40 address 0x44 |
4. Programming and Debug
Primary path: USB-C native USB Serial/JTAG.
- Connect USB-C cable.
- If the device enumerates, run
pio run -t upload. - If upload fails, hold SW1 BOOT, tap SW2 RESET, release SW2, release SW1, then upload again.
- Open serial monitor at 115200 baud.
- If native USB is unavailable, use UART recovery pads: TP7=
UART_TX, TP8=UART_RX, TP4=GND, TP3=3V3 reference.
5. Functional Validation
Table
| Test | Components | Input | Expected Output | Pass Criteria |
|---|---|---|---|---|
| USB power attach | J1, R1/R2, U1 | USB-C 5 V source | VBUS_PROT enabled | TP2 within 5 V range |
| Buck conversion | U2, L1, C4-C7 | VBUS_PROT | 3V3 | TP3 3.20-3.40 V |
| ESP32 boot | U3, R9/C10/SW2 | 3.3 V rail | Serial boot output | USB serial appears |
| SHT40 read | U4, R12/R13 | Firmware I2C transaction | T/RH values | plausible ambient reading |
| Status LED | U3, R14, D3 | Firmware blink | Visible blink | LED toggles without heating sensor area |
| Fault inputs | U1 FLT, U2 PG | Normal power | Logic high | firmware reports healthy |
| Wi-Fi | U3 | firmware credentials | STA connects | IP address printed |
| BLE | U3 | BLE firmware example | advertises | visible in BLE scanner |
6. Layout/Prototype-Specific Checks
- Confirm ESP32-C3 antenna overhang/keepout follows Espressif guidance.
- Confirm no copper or components under antenna keepout on any layer.
- Confirm SHT40 is placed at board edge or thermally isolated from U2/L1/U3/J1/D3.
- Confirm D1 and D2 ESD return paths are short and directly tied to ground near J1.
- Confirm U2 switching loop is compact and SW node copper is small.
Pass/Fail Summary
Table
| Section | Result | Notes |
|---|---|---|
| Visual inspection | [ ] Pass / [ ] Fail | |
| Power rails | [ ] Pass / [ ] Fail | |
| Critical signals | [ ] Pass / [ ] Fail | |
| Programming | [ ] Pass / [ ] Fail | |
| Sensor function | [ ] Pass / [ ] Fail | |
| Wireless function | [ ] Pass / [ ] Fail |
Board status: [ ] Ready for layout validation / [ ] Requires schematic or assembly rework
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signal Verification
4. Programming and Debug
5. Functional Validation
6. Layout/Prototype-Specific Checks
Pass/Fail Summary
