Safety gate: Do not connect a Li-ion/Li-poly cell, USB host, or unrestricted supply until Sections 2–5 pass. The battery chemistry, allowed voltage range, polarity, capacity, U10/U13 XC6209 output variants, and acceptable board current limits are not specified in the project and remain TBD.

• USB input/data: micro-USB U5, VBUS, D_P, D_N, CH340E U6.
• Battery/charging/power selection: battery header J1, charger U11 MCP73831T-2ACI/OT, mux U9 TPS2115APWR, VBAT, VBUS, VCC.
• Regulation: XC6209 regulators U10 (VCC → +3V3) and U13 (VCC → 3V3_2). Exact regulator suffixes/output voltages are TBD.
• Compute/programming: TTGO/ESP32 module U7, EN, FLASH, TX, RX.
• Display: GC9A01 assembly U4, 3V3_2, SCK, MOSI, TFT_CS, TFT_DC, TFT_RST, LEDK.
• RTC/sensors: DS3231MZ U1; BMA400 U2; shared SDA/SCL; interrupts RTC_INT, IO34, IO35.
• Human I/O: SW1, SW2, SW4, SW5; green LED D1; connector J1.

1. Verify PCB revision/serial and assembly traveler; photograph top and bottom.
2. Confirm the custom circular/round board outline is clean, without delamination, burrs, exposed internal copper, or damaged edge features.
3. Inspect all 51 fitted footprints for missing, tombstoned, shifted, cracked, overheated, or bridged parts.
4. Inspect fine-pitch devices especially: U2 LGA-12, U6 MSOP-10, U9 TSSOP-8, U1 SOIC-8, U11/U10/U13 SOT-23-5, Q1 SOT-23, module U7, and bottom-side display U4.
5. Inspect micro-USB U5 shell, tongue, contacts, anchor joints, edge alignment, and mechanical retention.
6. Inspect side buttons SW1, SW2, SW4, SW5 for coplanarity, free travel, edge clearance, and solder fillets.
7. Inspect battery header J1; verify pin 1 is physically identified before attaching a cell (J1.1 = VBAT, J1.2 = GND).
8. Confirm no solder balls/debris under U7 or U4; inspect exposed vias and copper for accidental shorts.
9. Verify display flex/module orientation and that U4 is intentionally on the bottom side; verify no mechanical interference.
10. PASS only if every joint is inspectable/acceptable and no bridge, polarity ambiguity, cracked component, or damaged connector is found.

• Probe ground at U5:GND or shell only after shell connection is verified, J1.2, and accessible ground pads at C1.1, C2.2, C3.2, C4.2, C5.2, C6.2, C16.2, C17.2, C18.2, C19.2, C22.2.
• PASS: all intended GND points show low, stable continuity; no intermittent response when connectors/buttons are gently stressed.

• U5:D+ ↔ U6:UD+ (D_P); U5:D- ↔ U6:UD- (D_N).
• U6:TXD ↔ U7:RX (RX); U6:RXD ↔ R4.1, then R4.2 ↔ U7:TX (TX, with R4 = 470 Ω).
• U7:IO18 ↔ U4:SCK; U7:IO23 ↔ U4:SDI; U7:IO05 ↔ U4:~CS; U7:IO12 ↔ U4:D/C; U7:IO33 ↔ U4:~RESET.
• U7:IO21 ↔ U1:SDA ↔ U2:SDX; U7:IO22 ↔ U1:SCL ↔ U2:SCX.
• U1:~INT/SQW ↔ U7:IO32 (RTC_INT); U2:INT1 ↔ U7:IO34; U2:INT2 ↔ U7:IO35.
• J1.1 ↔ U11:VBAT ↔ U9:IN1 (VBAT); U5:VBUS ↔ U11:VDD ↔ U9:IN2 (VBUS); U9:OUT ↔ U10:VIN/U13:VIN (VCC).
• PASS: intended endpoints are continuous and adjacent unrelated pads/nets are not shorted.

1. Confirm R14 = 510 Ω from U9:ILIM to GND; calculated/current-limit expectation is TBD pending approved datasheet interpretation and design target.
2. Confirm U9:D1 = GND; U9:D0 = VBAT; U9:STAT = STAT_PWR, with R19 = 220 kΩ from VCC to STAT_PWR.
3. Confirm bulk/decoupling: C5,C6 = 100 µF on VCC; C14,C15 = 0.1 µF on VCC; C16 = 4.7 µF and C18 = 0.1 µF on +3V3; C17 = 4.7 µF and C19 = 0.1 µF on 3V3_2; C1 = 4.7 µF and C3 = 0.1 µF on VBUS; C2 = 4.7 µF and C4 = 0.1 µF on VBAT.
4. Confirm U11:PROG uses R15 = 5 kΩ to GND. Expected charge current is TBD until formally derived/approved; do not infer a production limit from resistor value alone in this plan.
5. Confirm charge indicator path: VBUS → R13 470 Ω → D1 anode; D1 cathode → U11:STAT.
6. With a current-limited source and no battery, verify no unintended voltage appears at J1 beyond the charger’s intended behavior; acceptable value TBD.
7. With a simulator/battery emulator (not an unprotected cell), validate U11 charge states and measure charge current. PASS only against approved battery and charger limits, currently TBD.
8. Confirm exact U10/U13 XC6209 ordering codes and nominal outputs before accepting +3V3/3V3_2 as 3.3 V rails.
9. Design concern to resolve before battery qualification: U1:VBAT is tied to +3V3, not the board VBAT net. Verify this is intentional and within the RTC backup-input requirements.

1. Confirm U7:3V3 is on +3V3; verify all three GND pins (1, 15, 38).
2. Confirm reset: R8 = 10 kΩ pulls EN to +3V3; SW4 pulls EN to GND when pressed.
3. Confirm boot: R9 = 10 kΩ pulls FLASH to +3V3; SW5 pulls FLASH/U7:IO00 to GND when pressed.
4. Connect USB; confirm CH340E U6 enumerates as a serial device. Record VID/PID/port and driver version.
5. Capture reset boot log on RX/TX; baud and expected text are TBD.
6. Enter programming mode using SW5 + SW4 as required; flash a known integrity-test firmware. Toolchain, board target, flash parameters, and image hash are TBD.
7. Verify firmware can reboot repeatedly, report reset reason, and expose a build ID.
8. Exercise STAT_PWR at U7:IO15, B_MON at U7:IO25, and PIN_LED at U7:IO09; expected ADC/logic values are TBD.
9. PASS: repeatable USB programming, clean boot, no brownout/reset loop, and stable serial I/O.

1. Mechanical retention and shell inspection pass.
2. Confirm continuity and absence of shorts on D_P/D_N; verify pair is not swapped.
3. Confirm U6:VCC and U6:V3 are both connected to +3V3, with C9 = 0.1 µF from rail to GND.
4. Check protected-hub enumeration, disconnect/reconnect, cable reversal where applicable to micro-B (plug reinsertion), and gentle connector stress.
5. Run sustained serial loopback/transfer test for a duration and baud rate TBD; require zero framing/data errors.
6. Measure VBUS droop and board current during enumeration/programming; limits TBD.
7. Inspect USB routing/manufacturing evidence. No controlled-impedance or differential-pair net properties are present for D_P/D_N; treat signal-integrity compliance as OPEN.
8. U5:ID and U5:SHIELD are single-pin/unconnected nets. Verify intentional treatment, ESD/EMI strategy, and chassis/ground policy.

1. Confirm U4:VDD = 3V3_2; all four GND pins connect to GND.
2. Verify control/data continuity: SCK, MOSI, TFT_CS, TFT_DC, TFT_RST as listed in Section 4.
3. Verify backlight path: 3V3_2 → R1 22 Ω → U4:LEDA; U4:LEDK → Q1:D; Q1:S → GND; gate network PIN_LED through R21 10 kΩ with R22 1 MΩ to GND.
4. Bring up with backlight initially off; issue hardware reset and read/observe initialization response where supported. Driver settings, SPI frequency, and command sequence are TBD.
5. Enable backlight gradually by firmware control if PWM is used; measure 3V3_2 droop and backlight current. Limits TBD.
6. Display solid red/green/blue/white/black, checkerboard, gradients, text, and moving graphics. PASS: correct orientation/color order, no persistent lines/flicker/tearing beyond approved criteria, and no intermittent connector behavior.
7. Run display update continuously during soak test and monitor U13/Q1/R1 temperature.
8. Open ERC issue: U4:VDD is reported “power input not driven” even though it is on 3V3_2; resolve power-source modeling or confirm an actual electrical problem before release.

1. Confirm identity/orientation and C11 = 0.1 µF decoupling on +3V3.
2. Verify SDA/SCL, pull-ups R6/R7 = 1 kΩ to +3V3, and interrupt RTC_INT with R18 = 2.2 kΩ to +3V3.
3. Scan I²C and record detected address; expected address is TBD until approved from datasheet/firmware configuration.
4. Read/write time/date registers; power-cycle and compare retained time. Allowed drift and retention duration are TBD.
5. Configure interrupt/alarm/SQW behavior on RTC_INT; verify U7:IO32 transition and clear sequence.
6. U1:32KHZ and U1:~RST are intentionally shown as unconnected/single-pin nets; verify against product requirements.
7. Critical review: U1:VBAT is connected to +3V3. Determine whether backup operation is intended, whether a separate backup source is required, and whether the current connection is valid before acceptance.

1. Confirm LGA orientation and board-axis mapping; photograph pin-1 mark.
2. Verify U2:VDD and VDDIO on +3V3; GND and GNDIO on GND; C13 = 0.1 µF decoupling.
3. Current wiring sets U2:SDO to GND and U2:CSB to +3V3; verify this selects the intended I²C mode/address. Expected address is TBD pending approved datasheet check.
4. Verify SDX = SDA, SCX = SCL, INT1 = IO34, INT2 = IO35; U2 NC pins remain unconnected.
5. I²C scan, chip-ID read, soft reset, self-test (if supported), static 1-g orientation checks on each axis, and motion/interrupt tests. Exact register values, tolerances, ODR, ranges, and thresholds are TBD.
6. PASS: repeatable identification, plausible axis response/orientation, and both interrupt paths observed by U7 without bus lockups.

• SW1: pulls BTN2/U7:IO10 to +3V3 when pressed; R10 = 10 kΩ pulls BTN2 to GND when released.
• SW2: pulls BTN3/U7:IO13 to +3V3 when pressed; R11 = 10 kΩ pulls BTN3 to GND when released.
• SW4: pulls EN to GND; R8 = 10 kΩ pulls up to +3V3.
• SW5: pulls FLASH/U7:IO00 to GND; R9 = 10 kΩ pulls up to +3V3.

• Confirm polarity and R13 = 470 Ω series path from VBUS to D1:A; cathode is controlled by U11:STAT.
• Verify off/on/charge-status indications using a battery emulator. Expected patterns and brightness are TBD.

• Pinout: J1.1 = VBAT, J1.2 = GND.
• Verify mating connector polarization, battery lead polarity, strain relief, and current rating. Exact connector MPN and battery specification are TBD.

• Custom board ~36.13 mm × 36.13 mm, Standard 4 Layer stackup.
• Default trace width 0.25 mm; imported minimum trace width 0.152 mm; default keepout/clearance rule 0.2 mm.
• Through vias include 0.8/0.4 mm, 0.6858/0.3302 mm, and 0.6/0.3 mm configurations.
• Layout contains 524 route segments, 126 smart vias, 134 via nodes, two zones, and one fill.

1. Re-run all ERC/DRC after any design change; archive results.
2. Resolve all five reported airwire errors (currently identified as 2, 7b1dd2fa, 2, Trace c053, and Trace d1f0) and five dangling traces (Trace 06af, Trace 3f4f, Trace 8669, Trace c424, Trace cee4).
3. Resolve four component-overlap warnings: R7/SW2, SW1/R18, SW4/C9, SW4/U6.
4. Confirm/resolve reported outside-board bodies: U7, U5, SW1, SW2, SW4, SW5. Edge overhang may be intentional, but pads must remain manufacturable and mechanical drawings must approve it.
5. Resolve critical board-density finding. Tool reports 98.7% component-area fill and recommends bottom-side overflow; this metric may overcount board-edge parts, but remains an explicit review error.
6. Review decoupling-loop warnings for C17, C19, C22, C3, C4, C5, C6 and improve placement/return paths or document measured justification.
7. Resolve schematic symbol collisions (C15/C6, C14/C5, U11/R15, R21/Q1, U1/R18) and schematic wire/symbol collisions; these impede review even if PCB connectivity is correct.
8. Resolve ERC missing-power findings: U4:VDD not driven and U7:VP not connected. If U7:VP is intentionally unused, mark/document it correctly; if it is a required module pin, correct the circuit.
9. Assign traceable manufacturer part numbers to the 28 currently flagged passive/value-only items before production release.
10. Verify copper-to-edge, solder-mask slivers, annular rings, drill sizes, via aspect ratios, paste apertures, thermal reliefs, silkscreen readability, fiducials, panelization/tooling, impedance needs, and assembler capabilities. Acceptance limits/fabricator are TBD.
11. Verify D_P/D_N geometry and return path. Differential impedance target and tolerance are TBD and not declared in current net properties.
12. Generate fabrication outputs and run independent Gerber/ODB++ and pick-and-place review only after DRC closure.

1. Flash integrity-test firmware that cycles display patterns, reads RTC/BMA400, exercises interrupts/buttons, logs resets/errors, and varies backlight activity.
2. Record current at minimum in: power-off/leakage, reset, boot, idle display off, idle display on, active display update, USB serial transfer, sensor sampling, and battery-charge states. Limits are TBD pending an approved power budget.
3. Soak duration, ambient range, and pass limits are TBD. Suggested evidence categories (not acceptance values): supply current min/avg/max, each rail min/max/ripple, component temperatures, reset count, USB errors, I²C errors, display errors, RTC drift, and button events.
4. Repeat source transitions: USB-only ↔ battery-emulator-only ↔ both connected. Verify no reset or backfeed beyond approved criteria.
5. Perform repeated cold boots and warm resets; cycle USB insertion and all buttons.
6. PASS only with zero unexplained resets/bus lockups, no progressive heating, no rail excursions outside approved limits, and all measured currents within the approved power budget.

1. ERC errors: U4:VDD reported as undriven on 3V3_2; U7:VP reported unconnected.
2. PCB connectivity: five airwire errors are present (current check IDs: 2, 7b1dd2fa, 2, Trace c053, Trace d1f0); five dangling traces are identified (Trace 06af, Trace 3f4f, Trace 8669, Trace c424, Trace cee4). Exact airwire nets/endpoints require PCB repair inspection.
3. PCB overlaps: R7/SW2, SW1/R18, SW4/C9, and SW4/U6.
4. Outside-board warnings: U7, U5, SW1, SW2, SW4, SW5; intentional edge placement is not yet formally documented.
5. Board density: automated review reports critical 98.7% component-area fill.
6. Decoupling-loop warnings: C17, C19, C22, C3, C4, C5, C6.
7. Manufacturing traceability: 28 passive/value-only components currently lack manufacturer part numbers.
8. Schematic readability/errors: five symbol-body collisions plus wire/symbol and label collisions are reported; these can hide connectivity mistakes.
9. RTC backup architecture: U1:VBAT is tied to +3V3, not VBAT; intent and validity are unresolved.
10. Regulator identity: U10 and U13 are only specified as XC6209; exact output variants are absent, so expected rail values cannot be verified from the BOM.
11. USB SI: D_P/D_N lack declared differential-pair/controlled-impedance properties; target impedance and tolerance are TBD.
12. USB connector unused pins: U5:ID and U5:SHIELD are unconnected; shield/ESD/EMI intent is unresolved.
13. Battery interface: battery chemistry, voltage, capacity, connector exact MPN/polarization, protection strategy, and approved charge/current limits are TBD.
14. Electrical ratings: capacitor voltage ratings and most passive procurement identities are unavailable.
15. Acceptance values: staged supply limits, normal/peak current budget, rail tolerances/ripple limits, thermal limits, firmware image/toolchain, communication speeds, soak duration, and environmental limits are TBD.