Power Distribution Network Review

flux

1:45

Next gen (beta)
Project
Review (ERC/DRC)

Using Review (ERC/DRC) Tool.

Below is a focused PDN (Power Distribution Network) schematic review based on your current schematic nets and parts. I’ve organized it rail-by-rail, mapping sources to loads, noting decoupling/bulk practices, ground/reference strategy, sequencing/supervision, and basic protection. I also highlight critical gaps flagged by the DRC “Airwires” results, since many power nodes are still not fully wired.
High-level summary
Note on connectivity status
  • The DRC shows 222 “Airwires” errors, including many power pins and decouplers. Many observations below are about intent and what’s placed, with recommendations to finish connections and align values/layout to best practices.
Rail-by-rail findings
  1. USB input / VBUS front-end (Net 25, Net 45, Net 117)
  1. PMIC core rails (U5 DA9062) Likely rails from U5 mapping (based on nets):
  • 1.1 V core (Net 9 via /ryanf/CT%20Scanner%20DAS%20Board%209fae to /ryanf/CT%20Scanner%20DAS%20Board%209fae, feeding /ryanf/CT%20Scanner%20DAS%20Board%209fae and decoupling /ryanf/CT%20Scanner%20DAS%20Board%209fae, /ryanf/CT%20Scanner%20DAS%20Board%209fae).
  • 1.8 V (Net 10 via /ryanf/CT%20Scanner%20DAS%20Board%209fae to /ryanf/CT%20Scanner%20DAS%20Board%209fae), powering U4 VPP_2V5? and possibly I/O ref nets via LDO2 (Net 20).
  • 3.3 V (Net 115 via /ryanf/CT%20Scanner%20DAS%20Board%209fae and /ryanf/CT%20Scanner%20DAS%20Board%209fae filters), feeding U8 VDD/VDDUSB and most 3.3 V loads.
  • 1.8 V I/O (Net 40 via /ryanf/CT%20Scanner%20DAS%20Board%209fae), feeding U4 SPI_Vccio1, VPP_2V5, plus BME280 VDDIO and U8 VDD/VDDA portals shown on that net; this looks inconsistent (see below). Observations:
  • Many DA9062 pins (VLX, VBUCKx, VDD_BUCKx, VBBAT, etc.) have placed inductors and capacitors but numerous incomplete connections per Airwires. Ensure every buck has:
    • Correct inductor value/current rating and saturation headroom.
    • Input and output capacitors sized per DA9062 datasheet for stability and transient response.
    • Short loops and shared grounds via solid planes.
  • Net 40 labeling/mapping issue: It carries 1.8 V buck output but also tags U8 VDD, VDDA, and many decouplers. STM32 VDD/VDDA are 3.3 V typical; mixing them on a 1.8 V net is a logical error. This looks like either mislabeled portals or unintended connections. Needs correction before layout.
  • Net 18 looks like a 3.3 V digital rail feeding U4 I/O banks, oscillator VDD, and multiple decouplers. Confirm rail intent (name it VCC3V3_DIG) and separate from analog 3.3 V (AVCC3V3) with RC/inductor as needed.
  • Recommendations:
    • Resolve net intent and naming: separate 3.3 V digital (MCU/FPGA I/O), 3.3 V analog (ADC analog), 1.8 V rails (core or I/O), and 1.1 V core. Rename nets to explicit names and remap portals.
    • For each DA9062 buck: finalize L/C values per load and stability tables; place output bulk close to inductor, multiple 0.1 uF/1 uF ceramics near each IC VDD pin cluster.
    • Add test points (already a PMIC_TP exists) on each rail for probing and bring-up.
  1. 3.3 V rail(s) (Net 115, Net 18, AVCC3V3 portals)
  • Net 115 includes U8 VDDUSB, U5 VDDIO, BME280 VDD, multiple bulk/decoupling caps, and L4/L5 filters. Likely the main 3.3 V.
  • Net 18 shows DVDD for ADC [DDC232], FPGA VCCIO banks, oscillator, and many decouplers. This is also 3.3 V digital by content.
  • AVCC3V3 portals feed U1 DVDD and other analog sections through LC and bulk ([C7], [C8], [C41], [C42], [C38] etc.).
  • Good practice: isolate analog 3.3 V for ADC with an LC or RC filter from the noisy 3.3 V digital domain; you have inductors [L5] and LC here. Ensure the inductor values and output capacitance meet the ADC PSRR and transient needs.
  • Recommendations:
    • Consolidate naming to VCC3V3_DIG and AVCC3V3_ANA; verify that U8 VDDA is on the analog-clean 3.3 V rail with its own RC filter per STM32F7 datasheet.
    • Confirm total 3.3 V current budget: MCU (worst-case), FPGA I/O, sensors, oscillators, LEDs, plus ADC digital. Validate PMIC Buck capacity with margin.
    • Provide local 0.1 uF + 1 uF at each device VDD pin cluster; add 10 uF near rail distribution branches.
  1. 1.1 V core (Net 9 → VCC1V1)
  • Feeds /ryanf/CT%20Scanner%20DAS%20Board%209fae and has multiple local caps ([C45], [C46], [C33], [C34]) shown around U4.
  • Recommendation:
    • Verify U4 core current draw vs buck rating; ensure minimum output caps and low ESL/ESR ceramic near U4 pins.
    • Ensure VCCPLL decoupling ([C33], [C34]) is on the recommended rail (often 1.2 V/1.1 V clean with small RC). Airwires report VCCPLL blocked by auto-layout; ensure this rail is separate from noisy domains and has dedicated local decouplers.
  1. 1.8 V rails (Net 10, Net 20, Net 40)
  • Net 10 appears as a 1.8 V core/logic rail (VCCINT portal), sourced by Buck1 via [L2]; supplies U4 VPP_2V5? and LDO2 branch (Net 20 → AVCC1V8).
  • Net 20 shows U5 VLDO2 feeding AVCC1V8; good pattern for a cleaner analog 1.8 V branch.
  • Net 40 currently conflates 1.8 V with U8 VDD/VDDA and other nodes: this must be corrected.
  • Recommendations:
    • Keep analog 1.8 V (if used) on an LDO-filtered branch separate from digital 1.8 V.
    • Correct any accidental ties of U8 VDD/VDDA to 1.8 V; STM32F745 VDD/VDDA should be 3.3 V nominal.
  1. Precision reference and ADC front-end (Net 3 VREF = 4.096 V)
  • Chain: /ryanf/CT%20Scanner%20DAS%20Board%209fae → /ryanf/CT%20Scanner%20DAS%20Board%209fae buffering VREF to ADC /ryanf/CT%20Scanner%20DAS%20Board%209fae. Bypass and output caps present ([C3], [C1], [C4], [C5], [C10]) with LC filtering around AV rails feeding this subsystem.
  • The ADC also has QGND net separated via portal /ryanf/CT%20Scanner%20DAS%20Board%209fae and tied at U1 QGND pin: excellent. Ensure single-point tie to main GND near ADC per datasheet.
  • Recommendations:
    • Complete the exact decoupling topology per REF3140 and OPA350 datasheets (input/output caps, any stability constraints at the op-amp output with capacitive load).
    • Route VREF as a guarded, quiet trace with Kelvin connection to ADC VREF pin; place local 0.1 uF and 1 uF at the ADC VREF pin to ground (per ADC datasheet).
    • Ensure VREF source derives from the analog-clean 3.3 V rail and is not contaminated by digital transients.
  1. STM32F745 power (U8)
  • VDD, VDDA, VDDUSB on nets Net 40, Net 115; VCAP_1/2 with [C53], [C54], [C55], [C63], [C59]-[C62]. Airwires show some VCAP pins are not fully connected to their dedicated caps yet.
  • Recommendation:
    • Ensure all VCAP pins have the exact capacitance and ESR requirements per STM32F745 datasheet and are wired only to their caps and ground.
    • VDDA should have an RC filter from VDD and its own decoupling cluster.
    • VDDUSB must be 3.3 V; confirm it’s only on the 3.3 V rail with sufficient local decoupling.
  1. FPGA power (U4)
  • VCC (core) on Net 9 (1.1 V), VCCPLL (Airwires warnings), VCCIO banks on Net 18 and Net 40. Clock/oscillator [ASDM1-10MHz] powered from Net 18; ensure its decoupling caps close.
  • Recommendation:
    • Match VCCIO levels to interfacing devices (MCU, Flash, ADC digital). If MCU is 3.3 V, most VCCIO should be 3.3 V unless level-shifting is used.
    • Isolate VCCPLL with RC and give it dedicated 100 nF close to pins.
    • Ensure core rail transient capacity near the FPGA: add multiple 0.1 uF 0402 caps around the device perimeter plus 4.7–10 uF bulk nearby.
  1. SPI flash and sensor rails
  1. Ground and references
  • Single GND net is used widely with some analog discipline: QGND for ADC is separated and tied at U1. USB shield to ground via RC/ESD path indicated ([C17], [R12]).
  • Recommendation:
    • Confirm single-point connection strategy for QGND to GND and keep analog star-point near ADC reference return.
    • Stitch grounds generously around PMIC and high di/dt paths; keep VREF and ADC inputs away from switching current loops.
    • USB shield should connect to chassis/earth strategy; if not using chassis, use RC/ESD to signal ground as you’ve started.
  1. Sequencing, enables, supervision
  • DA9062 has many control pins present: ~ONKEY, ~RESET, ~RESETREQ, GPIOs; MCU BOOT0 and NRST nets are present with pull-ups/pull-downs.
  • Recommendations:
    • Use PMIC power-good rails to gate sensitive loads (e.g., release ADC and FPGA only after rails are in regulation).
    • Ensure MCU NRST pull and caps follow datasheet; verify BOOT0 resistor network for intended boot mode.
    • Consider adding a rail supervisor on the 3.3 V digital rail if PMIC doesn’t already assert a system-level reset with proper sequencing.
  1. Protection and EMC
  • USB input has Schottky but no upstream fuse or TVS; add polyfuse and VBUS TVS.
  • Add ESD diodes on all external connectors (USB D+/D−, CC, any user IO headers like /ryanf/CT%20Scanner%20DAS%20Board%209fae).
  • Consider common-mode chokes for sensitive clock/USB lines.
  • If CT DAS is a noisy environment, consider LC/T filters per rail branches that feed analog domains (ADC, VREF, sensors).
Key issues to resolve next
  1. Fix net intent/naming and misconnections:
    • Net 40 currently ties 1.8 V nodes and STM32 VDD/VDDA; split and correct.
    • Explicitly name rails: VDD_3V3_DIG, VDD_3V3_ANA, VDD_1V1_CORE, VDD_1V8_DIG, VDD_1V8_ANA, etc.
  2. Close all airwires on power pins and decouplers:
    • Especially U5 buck in/out loops, U8 VCAP pins, U4 VCCPLL and VCCIO banks, ADC DVDD/AVDD and VREF decouplers.
  3. Validate PMIC L/C selections and rail capacity:
    • Confirm peak and average current per rail (MCU, FPGA, ADC digital, IOs).
    • Confirm loop stability per DA9062 datasheet with your chosen inductors/caps.
  4. Strengthen input protection:
    • Add VBUS TVS, polyfuse, data-line ESD, and consider input LC.
  5. Analog cleanliness:
    • Keep VREF and ADC analog rails isolated via LC/RC filters, with star-ground at ADC.
    • Ensure STM32 VDDA has its RC and local caps.
  6. Decoupling completeness:
    • Per device pin clusters, place 1× 0.1 uF per power pin (or per pair) plus 1–4.7 uF bulk per side of large ICs; place as close as possible to pins.
If you want, I can propose exact L/C values per DA9062 rail and a decoupling spreadsheet for each device pin cluster, and then wire the nets accordingly.
161 days

Ready.

Sign up to send
VCC1V8
NRST
I2C_SDA
I2C_SCL
VCC3V3
BOOT
NRST
TDO/SWO
SPI_SI
I2C_SCL
LED_G
LED_B
LED_R
PMIC_SDA
PMIC_SCL
SPI_SS
I2C_SDA
SPI_SO
R24
Resistance
4.7k Ω
RST
R20
Resistance
100k Ω
R25
Resistance
4.7k Ω
R22
Resistance
330 Ω
R23
Resistance
330 Ω
C66
Capacitance
0.1u F
R21
Resistance
330 Ω
LED1
  • Ground
    Ground
    A common return path for electric current. Commonly known as ground.
    jharwinbarrozo
    20.5M
  • Net Portal
    Net Portal
    Wirelessly connects nets on schematic. Used to organize schematics and separate functional blocks. To wirelessly connect net portals, give them same designator. #portal
    jharwinbarrozo
    43.0M
  • Power Net Portal
    Power Net Portal
    Wirelessly connects power nets on schematic. Identical to the net portal, but with a power symbol. Used to organize schematics and separate functional blocks. To wirelessly connect power net portals, give them the same designator. #portal #power
    jharwinbarrozo
    11.4M
  • Generic Resistor
    Generic Resistor
    A generic fixed resistor for rapid developing circuit topology. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard resistor values: 1.0Ω 10Ω 100Ω 1.0kΩ 10kΩ 100kΩ 1.0MΩ 1.1Ω 11Ω 110Ω 1.1kΩ 11kΩ 110kΩ 1.1MΩ 1.2Ω 12Ω 120Ω 1.2kΩ 12kΩ 120kΩ 1.2MΩ 1.3Ω 13Ω 130Ω 1.3kΩ 13kΩ 130kΩ 1.3MΩ 1.5Ω 15Ω 150Ω 1.5kΩ 15kΩ 150kΩ 1.5MΩ 1.6Ω 16Ω 160Ω 1.6kΩ 16kΩ 160kΩ 1.6MΩ 1.8Ω 18Ω 180Ω 1.8KΩ 18kΩ 180kΩ 1.8MΩ 2.0Ω 20Ω 200Ω 2.0kΩ 20kΩ 200kΩ 2.0MΩ 2.2Ω 22Ω 220Ω 2.2kΩ 22kΩ 220kΩ 2.2MΩ 2.4Ω 24Ω 240Ω 2.4kΩ 24kΩ 240kΩ 2.4MΩ 2.7Ω 27Ω 270Ω 2.7kΩ 27kΩ 270kΩ 2.7MΩ 3.0Ω 30Ω 300Ω 3.0KΩ 30KΩ 300KΩ 3.0MΩ 3.3Ω 33Ω 330Ω 3.3kΩ 33kΩ 330kΩ 3.3MΩ 3.6Ω 36Ω 360Ω 3.6kΩ 36kΩ 360kΩ 3.6MΩ 3.9Ω 39Ω 390Ω 3.9kΩ 39kΩ 390kΩ 3.9MΩ 4.3Ω 43Ω 430Ω 4.3kΩ 43KΩ 430KΩ 4.3MΩ 4.7Ω 47Ω 470Ω 4.7kΩ 47kΩ 470kΩ 4.7MΩ 5.1Ω 51Ω 510Ω 5.1kΩ 51kΩ 510kΩ 5.1MΩ 5.6Ω 56Ω 560Ω 5.6kΩ 56kΩ 560kΩ 5.6MΩ 6.2Ω 62Ω 620Ω 6.2kΩ 62KΩ 620KΩ 6.2MΩ 6.8Ω 68Ω 680Ω 6.8kΩ 68kΩ 680kΩ 6.8MΩ 7.5Ω 75Ω 750Ω 7.5kΩ 75kΩ 750kΩ 7.5MΩ 8.2Ω 82Ω 820Ω 8.2kΩ 82kΩ 820kΩ 8.2MΩ 9.1Ω 91Ω 910Ω 9.1kΩ 91kΩ 910kΩ 9.1MΩ #generics #CommonPartsLibrary
    jharwinbarrozo
    1.5M
  • Generic Capacitor
    Generic Capacitor
    A generic fixed capacitor ideal for rapid circuit topology development. You can choose between polarized and non-polarized types, its symbol and the footprint will automatically adapt based on your selection. Supported options include standard SMD sizes for ceramic capacitors (e.g., 0402, 0603, 0805), SMD sizes for aluminum electrolytic capacitors, and through-hole footprints for polarized capacitors. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard capacitor values: 1.0pF 10pF 100pF 1000pF 0.01uF 0.1uF 1.0uF 10uF 100uF 1000uF 10,000uF 1.1pF 11pF 110pF 1100pF 1.2pF 12pF 120pF 1200pF 1.3pF 13pF 130pF 1300pF 1.5pF 15pF 150pF 1500pF 0.015uF 0.15uF 1.5uF 15uF 150uF 1500uF 1.6pF 16pF 160pF 1600pF 1.8pF 18pF 180pF 1800pF 2.0pF 20pF 200pF 2000pF 2.2pF 22pF 20pF 2200pF 0.022uF 0.22uF 2.2uF 22uF 220uF 2200uF 2.4pF 24pF 240pF 2400pF 2.7pF 27pF 270pF 2700pF 3.0pF 30pF 300pF 3000pF 3.3pF 33pF 330pF 3300pF 0.033uF 0.33uF 3.3uF 33uF 330uF 3300uF 3.6pF 36pF 360pF 3600pF 3.9pF 39pF 390pF 3900pF 4.3pF 43pF 430pF 4300pF 4.7pF 47pF 470pF 4700pF 0.047uF 0.47uF 4.7uF 47uF 470uF 4700uF 5.1pF 51pF 510pF 5100pF 5.6pF 56pF 560pF 5600pF 6.2pF 62pF 620pF 6200pF 6.8pF 68pF 680pF 6800pF 0.068uF 0.68uF 6.8uF 68uF 680uF 6800uF 7.5pF 75pF 750pF 7500pF 8.2pF 82pF 820pF 8200pF 9.1pF 91pF 910pF 9100pF #generics #CommonPartsLibrary
    jharwinbarrozo
    1.5M
  • Generic Inductor
    Generic Inductor
    A generic fixed inductor for rapid developing circuit topology. *You can now change the footprint and 3D model at the top level anytime you want. This is the power of #generics
    jharwinbarrozo
    15.1k
  • Terminal
    Terminal
    An electrical connector acting as reusable interface to a conductor and creating a point where external circuits can be connected.
    natarius
  • RMCF0805JT47K0
    RMCF0805JT47K0
    47 kOhms ±5% 0.125W, 1/8W Chip Resistor 0805 (2012 Metric) Automotive AEC-Q200 Thick Film #forLedBlink
    jharwinbarrozo
    1.2M
  • 875105359001
    875105359001
    10uF Capacitor Aluminum Polymer 20% 16V SMD 5x5.3mm #forLedBlink #commonpartslibrary #capacitor #aluminumpolymer #radialcan
    jharwinbarrozo
    1.2M
  • CTL1206FYW1T
    CTL1206FYW1T
    Yellow 595nm LED Indication - Discrete 1.7V 1206 (3216 Metric) #forLedBlink
    jharwinbarrozo
    1.1M

Inspect

CT Scanner DAS Board [No Net Type]

CT Scanner DAS Board [No Net Type]
Description

Created
Last updated by ryanf
1 Contributor(s)
ryanf

Controls

Properties

Availability & Pricing

DistributorQty 1
Arrow$92.88–$102.22
Digi-Key$127.74–$132.10
LCSC$318.38–$318.69
Mouser$129.78
TME$1.06
Verical$18.00–$22.80

Assets