Plant Monitoring PCB Design

flux

0:00

Work done
  • Refactored the schematic toward the new battery-powered sensor architecture: removed the orphaned load-switch section by deleting Q1, C17, C18, and redundant R6
  • Added missing schematic support parts: R14 for BQ24090 fast-charge programming, R15 and R16 for LED current limiting, and R17 / R18 for the second isolated mux channel pull-ups
  • Finalized key passive values/properties on R4, R5, R9, R12, R13, C6, and C19
  • Rewired the charger and sensor buses: U2 now has separate ISET / PRETERM / TS connections via R14, R9, and R4; U4 channel 0 and channel 1 now feed U5 and U6 on isolated downstream I2C nets instead of being shorted to 3V3
  • Fixed the ESP32-C3 control network: R5 is now a GPIO0 pull-up, and R3 now forms a real pull-up into the dedicated EN_CTRL net with C6, SW1, and U1
  • Rewired status indication so LED1 and LED2 now use sink-style status outputs with series resistors, and renamed the USB-C CC nets to CC1 and CC2
  • Connected the previously floating bulk cap C19 to 3V3, and tied the remaining exposed U1 ground pins to GND
  • Confirmed the current PCB is still on standard-4-layer, 1.30 mm with no project-specific layout rules yet; the old oversized rectangular layout remains and the fork outline has not been applied
  • Confirmed the current layout still has 84 airwires because PCB routing has not been completed
Success criteria review
  • ✅ Major schematic cleanup progressed substantially: charger programming, mux branch separation, LED current limiting, EN/IO0 fixes, and orphaned circuitry removal were applied
  • ✅ Key charger values were selected from the TI datasheet for U2: about 500 mA fast charge via R14 1.1 kΩ, 10% termination via R9 2 kΩ, and TS disable via R4 10 kΩ
  • ❌ I could not finish the remaining PCB work: fork outline update, 2-layer / 1.6 mm stackup conversion, layout rules, placement, routing, exposed electrode copper, and final DRC closure still remain
  • ❌ I also did not get to re-run and fully clear ERC after the latest wiring pass, so there may still be remaining no-connect or floating-pin warnings to resolve
Next steps
  • The next schematic step is a verification pass on U1, U2, U4, U5, and U6, then re-run ERC to confirm the remaining warnings are either fixed or intentionally marked NC.
  • After that, the natural next stage is PCB layout: board sizing, stackup, and component placement. I was not able to continue into that stage here, but once execution is available again I can proceed with the 32 × 75 mm fork-style layout, 2-layer / 1.6 mm FR4 stackup, and placement around the ESP32 antenna keepout and prong electrode region.
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PlantINT thumbnail
PROJECT OVERVIEW
Design a compact, battery-powered, IoT-connected plant monitoring PCB sensor node. The board combines WiFi/BLE connectivity, multi-sensor I2C acquisition, LiPo battery management with USB-C charging, and partially weatherproof design for outdoor/planter use.
The physical form factor is a FORK (forcina) shape: a wider rectangular head section (~32×30mm) housing all the electronics, and two narrow prongs (~10×45mm each, 8mm gap between them) extending downward to form the capacitive soil moisture electrodes. Reference: the shape resembles a plant stake that is pushed into soil.
I trust Flux AI's routing and placement judgment. Please apply your full expertise. The guidance below defines constraints — treat them as requirements, not suggestions.
BOARD SPECIFICATIONS
  • Layers: 2 (Top + Bottom copper)
  • Dimensions: Head 32×30mm + two prongs 10×45mm (total board ~32×75mm)
  • PCB thickness: 1.6mm FR4
  • Surface finish: ENIG (Electroless Nickel Immersion Gold) — MANDATORY Reason: the soil prong traces must be gold-plated for corrosion resistance
  • Min trace width: 0.15mm signal, 0.5mm power
  • Min clearance: 0.15mm
  • Soldermask: GREEN on both sides Exception: NO soldermask on the interdigital soil electrode traces on the prongs (the copper must be fully exposed to contact the soil)
  • Via: min hole 0.3mm, pad 0.6mm
  • 4× M2.5 mounting holes (2.7mm drill, 5mm annular copper ring) at corners of head section
  • Conformal coating keep-out zones: SHT40-AD1F-R2 (U8), VEML7700 (U2), soil electrode traces on prongs, USB-C connector J1
COMPLETE BILL OF MATERIALS
Active ICs
U1 — ESP32-C3-MINI-1 (Espressif, LCSC C2838502)
  • Main microcontroller: RISC-V 32-bit 160MHz, 4MB flash, 400KB RAM
  • WiFi 802.11b/g/n 2.4GHz + BLE 5.0
  • Package: SMD module 13.2×16.6×2.4mm, castellated edges
  • Operating voltage: 3.0–3.6V from VCC rail
  • I2C: SDA=GPIO8, SCL=GPIO9
  • USB: D+=IO19, D-=IO18
  • Status outputs: CHG_STATUS=IO2, PG_STATUS=IO3, LOAD_EN=IO4
  • CRITICAL placement: antenna area (rightmost ~3mm of module) must hang over board edge OR have copper keepout zone (no copper top or bottom under antenna area). This is mandatory for RF performance.
  • Add 100nF + 10µF decoupling on 3V3 pin, placed within 1mm of pin
U2 — VEML7700-TT (Vishay, LCSC C78606)
  • Ambient light sensor, 0.0036–120,000 lux, I2C address 0x10
  • Package: ODFN-6, 2.0×2.0×0.5mm
  • Operating voltage: 2.5–3.6V
  • Current: 90µA active, 0.2µA power-down
  • CRITICAL placement: position at TOP EDGE of head section, centered horizontally. The sensor photodiode window (top of package) must face upward toward the case lid. A transparent PMMA optical window (Ø10mm) in the case will be positioned directly above this IC. Leave 0mm clearance to board edge on that side if possible. The VEML7700 has ±45° field of view, so alignment does not need to be perfect, but centering under the window opening is preferred.
  • Add 100nF decoupling on VDD, placed within 1mm
U3 — SHT40-AD1B (Sensirion, LCSC C1550099) — INTERNAL sensor
  • Temperature + relative humidity sensor, I2C address 0x44
  • Package: DFN-4, 1.5×1.5×0.5mm — extremely small, requires careful pad design
  • Operating voltage: 1.8–3.6V
  • Current: 3.2µA per measurement (1ms active), 0.1µA sleep
  • PURPOSE: measures temperature and humidity INSIDE the case (ambient reference)
  • CRITICAL placement: position in CENTER of head section PCB, far from all heat sources. Minimum 8mm distance from BQ24090 (U6) and ME6211 (LDO1). The SHT40 chip surface IS the sensor — the hygroscopic polymer capacitor is on the top face of the IC. It must NOT be covered by conformal coating. However, for the internal sensor (U3), it can be in a slightly ventilated cavity inside the case to measure internal temperature drift compensation.
  • Add 100nF decoupling on VDD within 1mm
U8 — SHT40-AD1F-R2 (Sensirion, LCSC C5155469) — EXTERNAL sensor
  • Same electrical specs as U3 (SHT40 family), I2C address 0x44
  • Package: DFN-4 with integrated PTFE filter cap for dust/water protection The filter cap allows vapor to reach the sensor while blocking liquid water
  • PURPOSE: measures EXTERNAL ambient temperature and humidity (outside the case)
  • CRITICAL placement: position on the SIDE or BOTTOM EDGE of head section. This sensor must be accessible from outside the case through a ventilated chamber (labyrinth vent structure in case design). It must NOT be covered by conformal coating. The sensor's filter cap must face the vent opening direction. Minimum 10mm distance from BQ24090 and LDO thermal zone.
  • Connected via TCA9548A channel 1 (see below) — NOT directly on main I2C bus
U4 — FDC1004DGST (Texas Instruments, LCSC C266239)
  • 4-channel capacitance-to-digital converter, I2C address 0x50
  • Package: WSON-8, 2.0×2.0×0.8mm
  • Operating voltage: 3.3V
  • Current: 750µA active, 300nA shutdown
  • PURPOSE: reads capacitance of interdigital PCB traces immersed in soil. The IC itself is NOT the soil sensor — it measures the capacitance of external electrodes. CIN1 and CIN2 connect to the interdigital copper traces on the prong section.
  • CRITICAL placement: position at BOTTOM of head section, closest to prong entry point. This minimizes trace length to CIN1/CIN2, reducing parasitic capacitance pickup. Keep CIN1 and CIN2 traces short, wide (0.3mm+), shielded by GND guard rings on both sides of each trace. Route CIN1/CIN2 on the SAME layer (Bottom preferred) as the interdigital electrodes to avoid via parasitic capacitance.
  • SHLD1 and SHLD2 pins connect to GND (guard shield)
  • Add 100nF decoupling on VDD within 1mm
U5 — TCA9548A (Texas Instruments, LCSC C130026) — NEW COMPONENT vs previous schema
  • 8-channel I2C multiplexer, I2C address 0x70
  • Package: SOIC-24 or TSSOP-24, select smallest available footprint
  • Operating voltage: 1.65–5.5V
  • PURPOSE: MANDATORY to resolve I2C address conflict between U3 and U8, both of which have fixed address 0x44. Without this IC the two SHT40 sensors will collide on the bus and produce corrupt readings. Channel 0: connects to U3 (SHT40 internal) Channel 1: connects to U8 (SHT40 external) Main I2C bus (from ESP32): connects to TCA9548A upstream SDA/SCL
  • Add 100nF decoupling on VCC within 1mm
  • Reset pin (active low): connect to VCC via 10kΩ (always enabled) OR connect to a GPIO for software reset capability
U6 — BQ24090DGQT (Texas Instruments, LCSC C179663)
  • Single-cell LiPo/Li-ion battery charger, input 4.5–6.5V, charge voltage 4.2V
  • Package: DSBGA-9 (wafer-level), extremely small ~1.6×1.6mm
  • CRITICAL THERMAL: this IC dissipates up to 0.5W during charging. Place a copper thermal pad area ≥1cm² on BOTH layers under the IC. Add minimum 4 thermal vias (0.3mm hole, 0.6mm pad) under thermal exposed pad. Keep this IC at MAXIMUM distance from both SHT40 sensors. Thermal isolation: route at least 10mm of thin trace (~0.2mm) between BQ24090 thermal zone and any temperature-sensitive component.
  • ISET pin: connect to R3 (1.8kΩ) to set Icharge ≈ 494mA (C/4 for 2000mAh)
  • PRETERM pin: connect to R2 (5.1kΩ — keep existing value, sets termination threshold)
  • ISET2 pin: connect per datasheet recommendation (typically VSYS or VBAT)
  • TS pin: connect to R4 (10kΩ NTC thermistor or static resistor to GND) If using static resistor: 10kΩ to GND disables thermal protection RECOMMENDATION: add NTC 10kΩ B=3950 near battery for thermal protection
  • CHG# (open drain): connect to LED_RED via 330Ω to VCC, and to U1 IO2 via 10kΩ
  • PG# (open drain): connect to LED_GREEN via 330Ω to VCC, and to U1 IO3 via 10kΩ
  • OUT pin: VBAT rail (to battery positive and to LDO input)
LDO1 — ME6211C33M5G-N (Nanjing Micro One, LCSC C82942)
  • LDO regulator, Vin 2.0–6.0V → Vout 3.3V fixed
  • Package: SOT-23-5, 2.9×1.6mm
  • Quiescent current: 55µA (higher than MCP1700, but adequate)
  • Dropout: 300mV @ 100mA
  • CE pin: connect to VCC (always enabled) or to ESP32 GPIO for power gating
  • THERMAL NOTE: at full system load (~100mA), dissipation = (Vbat-3.3)×0.1 ≈ 40–90mW. Low risk, but keep minimum 5mm from SHT40 sensors.
  • Vin decoupling: C2 1µF + C1 100nF
  • Vout decoupling: C3 10µF (electrolytic or ceramic) + additional 100nF ceramic
O1 — SI2301CDS (Vishay, LCSC C10487)
  • P-channel MOSFET, Vds=-20V, Id=-3A, Vgs(th)=-0.4V typ
  • Package: SOT-23, 2.9×1.6mm
  • PURPOSE: load switch between VBAT and LDO1 input, controlled by ESP32 This allows the ESP32 to cut power to all sensors during deep sleep for maximum battery life (if desired — optional feature)
  • Gate connection: 10kΩ pull-up resistor from Gate to VBAT (MOSFET OFF by default)
    • GPIO IO4 from ESP32 drives Gate to GND through 1kΩ series resistor to turn ON IMPORTANT: this was missing from previous schema — gate must NOT float. Series 1kΩ on gate limits gate charge current and protects GPIO. Pull-up 10kΩ to VBAT ensures MOSFET stays OFF during ESP32 boot/reset.
  • Source: VBAT (battery positive)
  • Drain: LDO1 VIN
Connectors and Passive Components
J1 — USBC_C165948 (USB Type-C SMD receptacle, LCSC C165948)
  • USB-C connector for 5V power input and ESP32 programming
  • Position: TOP EDGE of head section (accessible when device is in soil)
  • VBUS pins → BQ24090 IN (via R_protection 1Ω/1A fuse resistor optional)
  • D+ → ESP32 IO19, D- → ESP32 IO18
  • GND → GND plane
  • All CC pins → GND via 5.1kΩ resistors (CC1: R_CC1 5.1kΩ, CC2: R_CC2 5.1kΩ) These are MANDATORY for USB-C to deliver 5V (tells charger it is a sink device) WITHOUT these resistors the USB-C port will NOT receive power from modern chargers.
U_BAT — LiPo 2000mAh connector
  • Use JST PH 2.0mm 2-pin connector (standard LiPo connector)
  • Position: head section, easily accessible for battery replacement
  • Polarity protection: the SI2301 load switch also provides polarity protection if wired with Source=Drain correctly (P-FET body diode blocks reverse current)
R1 — 4.7kΩ ±1% 0402 (CHANGED from 5.1kΩ in previous schema)
  • I2C SDA pull-up: connects VCC to SDA bus
  • Reason for change: 4.7kΩ is the standard I2C pull-up value per NXP I2C spec. 5.1kΩ causes slower rise times at 400kHz fast-mode, risking data errors.
R2 — 4.7kΩ ±1% 0402 (CHANGED from 5.1kΩ in previous schema)
  • I2C SCL pull-up: connects VCC to SCL bus
R3 — 1.8kΩ ±1% 0402
  • BQ24090 ISET: sets charge current to ~494mA (Ichg = 890/R3)
R4 — 10kΩ 0402
  • BQ24090 TS pin bias or NTC resistor (see BQ24090 notes above)
R5, R6 — 5.1kΩ 0402 (NEW — not in previous schema)
  • USB-C CC1 and CC2 pull-down resistors (MANDATORY for USB-C power delivery)
R7 — 10kΩ 0402 (NEW)
  • SI2301 Gate pull-up to VBAT
R8 — 1kΩ 0402 (NEW)
  • SI2301 Gate series resistor from ESP32 GPIO IO4
R9, R10 — 330Ω 0402 (NEW)
  • Current limiting for LED_RED and LED_GREEN (status LEDs)
C1 — 100nF 0402 X5R — LDO Vin decoupling C2 — 1µF 0402 X5R — LDO Vin bulk C3 — 10µF 0805 X5R — LDO Vout bulk C4 — 100nF 0402 — ESP32 VCC decoupling C5–C9 — 100nF 0402 — Per-IC VCC decoupling (one per U2/U3/U4/U5/U8) C10 — 4.7µF 0402 — BQ24090 IN bypass C11 — 4.7µF 0402 — BQ24090 OUT bypass
LED1 — Green 0402 — USB power good / charging complete indicator LED2 — Red 0402 — Charging in progress indicator
BTN1 — 3×3mm SMD tactile switch (optional, recommended)
  • Connected between ESP32 EN pin and GND, with 100nF debounce cap
  • Allows manual reset without USB for field use

ELECTRICAL NETS SUMMARY

Net NameDescriptionConnected to
VBUS_5VUSB-C 5V inputJ1 VBUS, BQ24090 IN
VBATBattery voltage 3.2–4.2VU_BAT+, BQ24090 OUT, O1 Source
VCCRegulated 3.3VLDO1 OUT, all IC VDD/VCC pins
GNDCommon groundAll GND pins, copper pour both layers
SDAI2C data (main bus)ESP32 IO8, TCA9548A SDA_A, VEML7700 SDA, FDC1004 SDA, R1 pull-up
SCLI2C clock (main bus)ESP32 IO9, TCA9548A SCL_A, VEML7700 SCL, FDC1004 SCL, R2 pull-up
SDA_CH0I2C mux channel 0TCA9548A SD0, SHT40-internal SDA
SCL_CH0I2C mux channel 0TCA9548A SC0, SHT40-internal SCL
SDA_CH1I2C mux channel 1TCA9548A SD1, SHT40-external SDA
SCL_CH1I2C mux channel 1TCA9548A SC1, SHT40-external SCL
SOIL_ASoil electrode set AFDC1004 CIN1, interdigital traces prong (even fingers)
SOIL_BSoil electrode set BFDC1004 CIN2, interdigital traces prong (odd fingers)
USB_DPUSB D+J1 D+, ESP32 IO19
USB_DMUSB D-J1 D-, ESP32 IO18
CHG_STATUSCharger statusBQ24090 CHG#, LED_RED, ESP32 IO2
PG_STATUSPower goodBQ24090 PG#, LED_GREEN, ESP32 IO3
LOAD_ENLoad switch controlESP32 IO4 via R8, SI2301 Gate
PARASITIC AND SIGNAL INTEGRITY CONSTRAINTS
Please consider the following parasitic effects when placing components and routing:
I2C bus parasitics: The I2C specification allows maximum 400pF total bus capacitance. With 4 devices on the main bus (ESP32, VEML7700, FDC1004, TCA9548A) plus the multiplexed sub-buses, keep total SDA/SCL trace length under 50mm. Route SDA and SCL as a parallel differential pair with 0.15mm clearance between them. Do not route I2C traces near switching power lines or under the antenna keep-out zone.
FDC1004 CIN1/CIN2 parasitic capacitance — CRITICAL: Any stray capacitance on CIN1/CIN2 traces directly offsets the soil measurement. Each picofarad of parasitic capacitance reduces measurement range. Requirements:
  • Keep CIN1/CIN2 trace length under 15mm from FDC1004 pins to prong entry point
  • Route on Bottom layer only, no layer changes (vias add ~0.5pF each)
  • Add copper guard ring (connected to SHLD1/SHLD2=GND) completely surrounding each CIN trace on the same layer — this shields the trace from external fields
  • Maintain 0.5mm spacing between CIN1 trace and CIN2 trace (and their guard rings)
  • The interdigital soil electrodes on the prongs: finger width 0.8mm, gap 0.8mm, finger length 25mm, approximately 15–20 alternating fingers per electrode These traces have NO soldermask (fully exposed copper, ENIG finish)
BQ24090 switching node: The BQ24090 is a linear charger, NOT a switching regulator, so there is no switching noise. However, it dissipates power as heat. The primary constraint is thermal, not EMI. Keep input/output bypass capacitors (C10, C11) within 2mm.
ESP32-C3 antenna zone: Mandatory keepout: no copper, no traces, no vias, no components in the area directly beneath and 3mm around the ESP32 module antenna. The antenna is on the left side of the module. Orient the module so the antenna faces toward the top or side edge of the board.
Power supply decoupling placement: All 100nF decoupling capacitors MUST be placed within 1mm of their associated VCC/VDD pin. The parasitic inductance of a longer connection nullifies the effect. Place decoupling on the same layer as the IC where possible. The 10µF bulk cap (C3) can be up to 5mm from the LDO output.
Thermal gradients and temperature sensor placement: The two SHT40 sensors measure temperature via an on-chip bandgap reference. Self-heating of nearby components creates a thermal offset error. Known heat sources on this board and their typical power dissipation:
  • BQ24090: up to 500mW during USB charging
  • ME6211 LDO: 40–90mW at typical load
  • ESP32-C3: 15–25mW in active mode (WiFi), 0.02mW in deep sleep Required minimum distances from any SHT40:
  • From BQ24090: ≥12mm (critical)
  • From ME6211 LDO: ≥8mm
  • From ESP32-C3: ≥5mm (less critical — low dissipation)
THERMAL MANAGEMENT REQUIREMENTS
The device will be used outdoors in ambient temperatures from -10°C to +50°C. The case is a sealed or semi-sealed plastic enclosure approximately 35×35×80mm. Internal temperature rise above ambient must be kept below +8°C during USB charging.
BQ24090 thermal design:
  • Thermal pad (exposed pad on DSBGA package): connect to copper area on both layers
  • Top layer: copper fill area ≥ 1cm² directly under and around IC
  • Bottom layer: mirrored copper fill area ≥ 1cm² connected via thermal vias
  • Minimum 4 thermal vias under pad: 0.3mm drill, 0.6mm pad, evenly distributed
  • These thermal vias conduct heat to bottom layer copper which acts as a heatsink
  • In the case design (outside scope of PCB): a thermally conductive pad between the PCB bottom copper and the plastic case back wall improves heat transfer
ME6211 LDO thermal design:
  • Low dissipation at typical 50–80mA load: (4.0V - 3.3V) × 0.075A ≈ 52mW
  • This is well within SOT-23 package limits (max ~300mW at 25°C ambient)
  • Standard copper pour around package is sufficient
  • No additional thermal vias required unless load consistently exceeds 150mA
Fire safety note: At no point should any trace carry more than its rated current. Power traces (VBAT, VCC) should be minimum 0.5mm for up to 500mA. The USB VBUS trace from J1 to BQ24090 carries up to 500mA — use 0.8mm trace. Add a polyfuse (PTC resettable fuse) 500mA on VBUS line between J1 and BQ24090 for short-circuit protection (LCSC C178886, 0805 package).
WEATHERPROOFING DESIGN GUIDANCE (for PCB layout decisions)
The board will be coated with conformal coating after assembly, EXCEPT:
  1. SHT40-AD1F-R2 (U8 external sensor) — the PTFE filter cap must remain uncoated
  2. VEML7700 (U2) — photodiode window must remain uncoated and unobstructed
  3. Interdigital soil traces on prongs — must remain bare copper (ENIG) for soil contact
  4. USB-C connector J1 — coating would block the port
  5. Battery JST connector — coating would block connector mating
For the PCB layout, implement the following to support weatherproofing:
  • Place U8 (SHT40 external) and U2 (VEML7700) in designated "coating exclusion zones" clearly marked on the silkscreen layer with dashed boundary lines
  • Add silkscreen labels: "NO COAT" next to U8 and U2
  • Add silkscreen label: "EXPOSED — SOIL ELECTRODES" on the prong traces
  • The board outline on the prong section must have no sharp corners — use R1mm rounded corners where prongs meet the head section to prevent cracking when the device is pushed into soil
INTERDIGITAL SOIL ELECTRODE SPECIFICATION (prong section)
The bottom two prongs of the board ARE the soil moisture sensor. Trace parameters for the interdigital (comb/fork) capacitive electrodes:
  • Layer: Bottom copper
  • Trace width: 0.8mm
  • Gap between adjacent fingers: 0.8mm
  • Number of fingers per electrode: 16 (8 connected to CIN1, 8 to CIN2, alternating)
  • Finger length: 25mm
  • Connection point: at the top of the prongs where they join the head section
  • Guard ring: GND copper guard ring around the entire interdigital pattern on Bottom layer
  • NO soldermask over any part of the interdigital pattern
  • The two electrodes (SOIL_A and SOIL_B) must be symmetrically distributed so that a uniform electric field forms between them when immersed in soil
  • Add stitching GND vias around the prong perimeter every 8mm
SILKSCREEN AND REFERENCE DESIGNATORS
All components must have visible reference designators on the silkscreen layer. Minimum text size 0.6mm height. Add the following board information:
  • Top left: "SmartPlant v1.0"
  • Top right: "riccardo.schiavo.1"
  • Date code placeholder: "DATE: ______"
  • Near J1: PIN 1 marker and "USB-C POWER + FLASH"
  • Near U8: "EXTERNAL SENSOR — NO COAT"
  • Near prong junction: "SOIL ELECTRODES — NO MASK — ENIG"
  • Near ESP32 antenna area: keepout boundary marker

I2C DEVICE MAP (for firmware reference)

AddressDeviceBusNotes
0x10VEML7700 (U2)Main I2CDirect connection
0x50FDC1004 (U4)Main I2CDirect connection
0x70TCA9548A (U5)Main I2CI2C multiplexer
0x44 ch.0SHT40 internal (U3)TCA9548A channel 0Via mux
0x44 ch.1SHT40 external (U8)TCA9548A channel 1Via mux
FINAL NOTES FOR FLUX AI
I trust Flux AI's judgment on:
  • Exact component placement optimization within the constraints above
  • Via placement and layer assignments for non-critical signals
  • Polygon fill strategy and via stitching density
  • Any minor trace re-routing needed to clear DRC errors
  • Silkscreen label exact positioning to avoid overlap with pads
Please prioritize in this order:
  1. Electrical correctness (no DRC errors, no antenna violations)
  2. Thermal management (BQ24090 copper, SHT40 distance from heat)
  3. Signal integrity (FDC1004 CIN guard rings, I2C trace length)
  4. Manufacturability (SMT assembly friendly, no isolated pads, no acute angles)
  5. Physical compactness within the fork shape outline
Generate a complete 2-layer PCB ready for Gerber export to PCBWay.

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