4S Lithium-Ion BMS Design
Worked for 37 mins 25 sec
I could not get the final localized DRC to 0 airwires with the available routing flow.
Completed:
- Preserved the clean 297 mm × 37 mm board, center slot, and all 8 M6 holes.
- Re-ran localized DRC.
- Nudged the B1/B2/B3 monitoring/filter area:
- Spread B1/B2/B3 terminals.
- Repositioned RVC1–RVC3 and CVC1–CVC3 to open routing channels.
- Specifically fixed the blocked RVC1 P2 escape condition.
- Deleted stale/overlapping local trace fragments around the RVC cluster.
- Ran autoroute, then a cleanup autoroute pass.
- Final localized DRC shows 0 overlapping copper errors.
Remaining:
- 4 airwire errors still remain.
- 3 are persistent B1/B2/B3-related route failures.
- 1 remains tied to the auto-generated fill/stitching artifact.
- 13 dangling-trace warnings remain after the second routing pass.
The board is improved and overlap-free, but it is not yet manufacturing-clean. The remaining items need true manual trace editing/stitch placement or a more capable scoped routing/manual copper tool rather than another autoroute pass.
Simplify placement
Document blockers
Check manufacturability
Adjust terminals
Export review package
Refine this doc
Ask about this doc
Board Bring-Up Plan — Prius 4S BM3451 BMS
Prerequisites
- Equipment: DMM, current-limited isolated bench supply or cell simulator, oscilloscope, thermal source, insulated probes, Toyota ECU harness simulator or isolated 12 V continuity tester.
- Safety: this board connects to a 4S Li-ion stack. Start with a current-limited cell simulator before connecting CATL modules. Keep the isolated fault loop floating; do not connect it to BMS GND.
- Target IC configuration: BM3451SMDC-T28A, TSSOP-28, 4S mode with SET tied to VCC_BM3451 and VC1 tied to GND/B-.
1. Visual Inspection
- Confirm U1 is fitted as BM3451SMDC-T28A TSSOP-28, not the placeholder library template identity.
- Confirm B-, B1, B2, B3, and B4 M4 sense pads are mechanically secure and isolated from adjacent copper.
- Confirm RBAL1–RBAL4 are 75 ohm, minimum 2 W parts with clearance for heat.
- Confirm ISO_CO and ISO_DO are phototransistor optocouplers and that FLT_A/FLT_B have no copper tie to GND or cell nodes.
2. Power and Cell Node Verification
Table
| Rail / Node | Source | Expected Voltage | Measure At | Current Limit | Pass Criteria |
|---|---|---|---|---|---|
| GND / B- | Cell stack negative | 0 V reference | B- pad, U1 GND/VC1 | 5 mA during simulator test | Stable reference, no short to isolated fault loop |
| B1 | Cell 1 positive | 2.8–4.225 V vs B- | B1 pad | 5 mA | Tracks simulator cell 1 within DMM tolerance |
| B2 | Cell 2 positive | 5.6–8.45 V vs B- | B2 pad | 5 mA | Tracks cells 1+2 sum |
| B3 | Cell 3 positive | 8.4–12.675 V vs B- | B3 pad | 5 mA | Tracks cells 1+2+3 sum |
| B4 | Cell 4 positive / pack+ | 11.2–16.9 V vs B- | B4 pad | 5 mA | Tracks 4-cell stack sum |
| VCC_BM3451 | B4 through RVCC | Approximately B4, filtered | U1 VCC / CVCC | 5 mA | Within small RVCC drop; CVCC stable |
Procedure:
- With no cells connected, measure resistance from B4 to GND and from FLT_A/FLT_B to GND; fault-loop resistance to GND should be open.
- Apply four equal simulated cells at 3.50 V each, current-limited to 5 mA per tap.
- Verify GND, B1, B2, B3, B4, and VCC_BM3451 in order.
- Increase one cell slowly to 4.225 V and verify the corresponding balancing path can activate near the BM3451 programmed OVP/balance behavior.
- Decrease one cell slowly to 2.800 V and verify DO fault behavior.
3. Critical Signal Verification
Table
| Signal | Net / Component | Expected State | Measure At | Notes |
|---|---|---|---|---|
| SET | U1 SET tied to VCC_BM3451 | High | U1 SET | Required for 4S mode |
| VC1 | U1 VC1 tied to GND | 0 V | U1 VC1 | Datasheet 4S requirement |
| NTC | RT1 / U1 NTC | Thermistor divider behavior | U1 NTC | Heat RT1 to validate thermal response |
| TRH | RTRH / U1 TRH | Reference from 7 k resistor | U1 TRH | Datasheet example threshold network |
| CO_FLAG | U1 CO / ISO_CO input | Changes on charge/OV fault | ISO_CO input | CO is open-drain; check pull behavior |
| DO_FLAG | U1 DO / ISO_DO input | Changes on discharge/UV fault | ISO_DO input | DO is CMOS output |
| BAL2–BAL5 gates | Q1–Q4 gates | Active for corresponding high cell | MOSFET gates | 4S datasheet mapping uses VC2–VC5/BAL2–BAL5 because VC1 is grounded |
4. Connector and Interface Tests
Table
| Connector / Pad | Type | Pins to Verify | Test Method |
|---|---|---|---|
| B-, B1, B2, B3, B4 | M4 sense pads | All five cell taps | Continuity to harness ring terminals and to U1 sense-filter networks |
| FLT_A / FLT_B | Isolated fault loop | Floating two-wire loop | Continuity changes only through optocoupler transistor outputs; no continuity to BMS GND |
5. Functional Validation
Table
| Test | Input | Expected Output | Pass Criteria |
|---|---|---|---|
| 4S mode selection | SET high, VC1 at GND | U1 interprets stack as 4S | No activity on grounded VC1 channel; active channels follow VC2–VC5 |
| Over-voltage | Raise one cell above 4.225 V beyond TOV delay | CO fault output changes; balance channel turns on | ISO_CO output loop state changes and bleed current appears |
| Under-voltage | Lower one cell below 2.800 V beyond TOVD delay | DO fault output changes | ISO_DO output loop state changes |
| Passive balancing | Raise active cell above balance threshold | One 75 ohm path conducts | Bleed current approx 50–60 mA near 4.05–4.225 V |
| Thermal protection | Heat RT1 | CO/DO fault behavior per datasheet threshold network | Fault loop changes at expected temperature window |
6. Expected Measurements Reference
Table
| Measurement | Location | Expected Value | Instrument |
|---|---|---|---|
| OVP threshold | Any simulated active cell | 4.225 V nominal | Cell simulator + DMM |
| UVP threshold | Any simulated active cell | 2.800 V nominal | Cell simulator + DMM |
| Balance threshold | Any active cell | 4.050 V nominal | Cell simulator + DMM |
| Bleed current | RBAL1–RBAL4 path | About 55 mA near 4.1 V | DMM current or resistor voltage |
| Isolated loop leakage | FLT_A/FLT_B to GND | Open circuit | DMM resistance |
Pass/Fail Summary
Table
| Test Section | Result | Notes |
|---|---|---|
| Visual Inspection | [ ] Pass / [ ] Fail | |
| Power and Cell Nodes | [ ] Pass / [ ] Fail | |
| Critical Signals | [ ] Pass / [ ] Fail | |
| Connector Tests | [ ] Pass / [ ] Fail | |
| Functional Validation | [ ] Pass / [ ] Fail |
Board Status: [ ] Ready for vehicle-level integration / [ ] Requires rework
Welcome 👋
Flux helps you build PCBs faster with an AI teammate!
Create your account to collaborate, stay updated, fork your own version, and get instant answers from our AI agent.