flux

#Goal

- Continue the redesign work for the Line Sorter project (excluding the spring‑cage terminal replacement) by implementing a 24 V input power tree with a new 12 V rail for the stepper and a 5 V (≥3 A) rail for servos/USB/IR. Integrate a StepStick (A4988/DRV8825) module, replace remaining I/O connectors with specified JST/Molex types, add a 470 uF bulk capacitor near the servos, enforce wide (20–30 mil) power and stepper traces, include thermal pours/vias for the buck regulators, verify logic-level compatibility and add shifters if needed, and run ERC/DRC and BOM updates.

#Implementation plan

1. Power Subsystem

1. Add a buck converter circuit to step down 24 V to 12 V for the stepper motor.

2. Add a separate buck converter to step down 24 V to 5 V ensuring it is rated for at least 3 A, powering servos, USB, and IR circuits.

3. Place and connect a 470 uF capacitor close to the servo rail to provide bulk decoupling.

2. Stepper Integration

1. Integrate the StepStick footprint for an A4988/DRV8825 module into the design.

2. Connect the STEP, DIR, ENABLE, and micro-stepping (MS1-3) signals. Ensure VMOT is connected to the new 12 V rail and VIO is connected based on compatible logic levels.

3. I/O Connector Replacement

1. Replace remaining I/O connectors with JST/Molex headers as specified.

2. Rewire connections for peripherals such as servos, IR (with necessary pull‑up resistor where applicable), and USB camera.

4. Routing and Layout Enhancements

1. Enforce 20–30 mil wide traces on power/stepper nets to handle higher currents.

2. Add copper thermal pours and incorporate thermal vias in the buck converter areas to aid in heat dissipation.

5. Verification and Documentation

1. Verify logic-level compatibility across all modules and add level shifters if required.

2. Run ERC and DRC checks and update the BOM to reflect component changes.

3. Preserve all existing net mappings where applicable to maintain PLC connections for later spring‑cage terminal replacement.

#Success criteria

- A complete schematic with accurate power trees and rail specifications (24 V, 12 V, 5 V rails) is available.

- The StepStick module is integrated with correct signal connections and voltage references.

- All legacy I/O connectors are successfully replaced with JST/Molex types.

- PCB layout features 20–30 mil trace widths on key nets and includes necessary thermal management via copper pours/vias.

- ERC/DRC checks yield no significant errors, and the BOM is updated accordingly.

- Logic level compatibility is validated, with shifters added if necessary.

Added 1x ST1S14PHR as U4

Added 1x TPS56339DDC as U5

Added 2x Generic Inductor as L2, L3

Added 6x Generic Capacitor as C3, C4, C6, C10, C11, C12

Added 1x B2P-VH(LF)(SN) as J1

Removed U5

Removed J1

⚠️ Removed components had their net connections destroyed. Use the connections tool with a `view` action to verify connectivity and re-wire any lost connections.

Connected J1:P1, U2:VIN, U2:EN, C3:P1, C4:P1, U5:VIN, U4:VIN to ^24V_IN

Connected J1:P2, U2:GND, C3:P2, C4:P2 to ^GND 2

Connected U5:GND, C10:P2, C11:P2, U4:GND, U4:PADGND, C6:P2, C1:P2, Servo1:Gnd, Servo2:Gnd, Servo3:Gnd, Servo4:Gnd, J4:2, J5:2, J6:Pin_1 to ^GND

Connected U5:SW, L2:P1 to ^BUCK12_SW

Connected L2:P2, C10:P1, C11:P1, J6:Pin_2 to ^12V_RAIL

Connected U4:SW, L3:P1 to ^BUCK5_SW

Connected L3:P2, C6:P1, C1:P1, Servo1:5v, Servo2:5v, Servo3:5v, Servo4:5v, J4:1, J5:1, R3:P2 to ^5V_RAIL

Connected J5:3, R3:P1 to ^IR_SIG

nets {

net Net 26 = J4:2, J6:Pin_1, J5:2, Servo4:Gnd, Servo3:Gnd, Servo2:Gnd, Servo1:Gnd, C1:P2, C6:P2, U4:PADGND, U4:GND, C11:P2, C10:P2, U5:GND, R18:P2;

net Net 10 = R26:P1, R25:P2, U2:FB;

net GND = C4:P2, C3:P2, J1:P2, D2:K, C5:P1, C2:P1, Up:P2, Down:P2, U5:GND, J1:P2, R6:P2, Q1:S, U1:3, R37:P2, Q7:S, J15:2, C8:P2, Q8:S, R39:P2, R24:P2, C7:P2, R41:P2, Q9:S, U2:GND, U3:V-, R26:P2, U1:4, Q6:S, R35:P2;

net Net 18 = J1:P1, D1:K, D2:A, U1:2, U2:VIN, U4:VIN, U5:VIN, C4:P1, C3:P1, Down:P1, U5:VI, C8:P1, J15:1, L1:P1, R25:P1, U2:EN;

net Net 5 = Up:P1, U3:V+, U5:VO;

net Net 22 = J4:1, R3:P2, J5:1, Servo4:5v, Servo3:5v, Servo2:5v, Servo1:5v, C1:P1, C6:P1, L3:P2, D9:A;

net Net 8 = L1:P2, U2:SW, C9:P2;

net Net 2 = J1:P1, F1:P1;

net Net 21 = J3:2, R17:P2;

net Net 17 = J3:1, D8:A;

net Net 9 = C9:P1, U2:BOOT;

net BUCK12_SW = U5:SW, L2:P1;

net 12V_RAIL = L2:P2, J6:Pin_2, C11:P1, C10:P1;

net BUCK5_SW = U4:SW, L3:P1;

net IR_SIG = J5:3, R3:P1;

}

Renamed Net 18 to 24V_IN

Renamed Net 22 to 5V_RAIL

Renamed 12V_RAIL to 12V_RAIL

⚠️ Rename to GND skipped: designator already exists (kept as Net 26)