The two-sided placement, 3D preview, and full reroute are complete and clean. One electrical limitation remains: both SETUP buttons are correctly paralleled, but GPIO14 is not exposed on the selected socketed DevKit headers, so the SETUP net cannot reach the ESP32 without a physical bodge/test-point wire or a different DevKit carrier.
Front: centered landscape TFT, joystick with MID on the left, horizontally aligned A/B on the right, and two centered SETUP buttons above/below the display.
Rear: centered USB-accessible DevKit, mirrored MAX98357A modules and audio passives, symmetric speakers, and preserved JST speaker polarity.
Board remains 180 × 100 mm, 4 layers. Routing and DRC are clean: 0 airwires, 0 dangling traces, overlaps, bounds, or keepout violations.
Open item
The two SETUP buttons are paralleled to GND on BTN_SETUP_GPIO14, but the socketed ESP32-C6 DevKit does not expose GPIO14 on its headers. The SETUP net therefore cannot reach the MCU through the existing sockets.
Next steps
Add a documented bodge/test-point connection from the DevKit’s GPIO14 pad to the PCB.
Alternatively assign SETUP to an exposed GPIO, such as GPIO15.
PRG32 PCB is a carrier for a replaceable Waveshare ESP32-C6-DEV-KIT-N8. The development board retains its USB-C programming and power path; the carrier adds no second USB-C input, battery, charger, or power-path circuitry. The board outline is locked at 180 × 100 mm with the Standard 4 Layer stackup. Placement is in scope; routing remains explicitly out of scope pending placement approval.
Functional blocks are the socketed MCU interface, confirmed TFT socket, one bare directional switch plus four tactile controls (A/B/SELECT/START), two socketed MAX98357A I2S amplifier breakouts, two speaker-only interfaces, and local bypassing. Resistive-touch functionality is deliberately not implemented.
Confirmed display socket
The user-confirmed product is Amazon ASIN B082QVKT7M, sold as a DollaTek 2.8-inch, 240×320 SPI resistive-touch TFT with microSD interface. Its published product data identifies an ILI9341 display controller, 86 × 50 mm module outline, 240×320 resolution, white-LED backlight, and compatibility with 3.3 V or 5 V logic/supply arrangements. The matching LCDWIKI MSP2807 documented module provides the same 14-pin silkscreen sequence and is used as the safe socket-interface evidence.
J5 is a 1×14 female through-hole 2.54 mm socket (Flux library part: Pin Socket 01x14 2.54mm Vertical). The documented compatible module lists a 3.3–5 V VCC input, 3.3 V TTL logic, a 4-wire SPI ILI9341 TFT controller, and 0.31 W power consumption. The stated 50.0 × 86.0 mm PCB outline closely matches the Amazon 50 × 86 mm claim. The user supplied the required physical measurements for the actual module: 50.00 × 86.00 mm overall PCB, 43.20 × 57.60 mm active display, 50.00 × 69.20 mm LCD/backlight assembly, 44.00 × 76.08 mm mounting-hole center pattern, four Ø3.20 mm holes with Ø4.70 mm clearance/pad diameter, 1.60 mm PCB thickness, and a 1×14 header at 2.54 mm pitch (33.02 mm contact span).
Table
J5 pin
Module label
Carrier connection
Status
1
VCC
3V3
powered from the ESP32 dev-board 3.3 V regulator
2
GND
GND
connected
3
CS
TFT_CS_GPIO10
source-defined TFT bus
4
RESET
TFT_RST_GPIO0
source-defined TFT bus
5
DC/RS
TFT_DC_GPIO1
source-defined TFT bus
6
SDI/MOSI
SPI_MOSI_GPIO7
source-defined TFT bus
7
SCK
SPI_SCLK_GPIO6
source-defined TFT bus
8
LED
GPIO5_TFT_BL
active-high documented backlight control
9
SDO/MISO
SPI_MISO_GPIO2
TFT readback
10
T_CLK
—
intentionally no-connect; touch not supported
11
T_CS
—
intentionally no-connect; touch not supported
12
T_DIN
—
intentionally no-connect; touch not supported
13
T_DO
—
intentionally no-connect; touch not supported
14
T_IRQ
—
intentionally no-connect; touch not supported
Although the Amazon listing says the board includes an SD interface, no SD chip-select signal appears on this 14-pin header; no undocumented SD connection was made.
Voltage choice and power budget
J5 VCC is connected directly to 3V3, not 5V. This uses the module’s documented 3.3 V VCC capability and matches its documented 3.3 V TTL interface; therefore, no level shifter is needed between the ESP32-C6 3.3 V GPIOs and this socket. C6 (100 nF, 10 V X7R ceramic) and C7 (10 µF, 10 V X7R ceramic) provide local high-frequency and bulk bypassing at the J5 supply connection.
The documented 0.31 W display consumption corresponds to a conservative 0.094 A at 3.3 V (0.31 W ÷ 3.3 V). The Waveshare board schematic identifies an SGM2212-3.3V, 800 mA LDO feeding the board 3.3 V rail. The ESP32-C6 module requires an external supply capable of 0.5 A; the carrier 3V3 net is therefore annotated at 0.594 A expected budget (0.500 A + 0.094 A) and 0.800 A source rating. This has 0.206 A nominal margin, but the 0.31 W display figure has no stated test condition or maximum-current limit; validate measured peak current before a release.
Table
Rail
Load/basis
Current annotation
3V3
ESP32-C6 0.500 A requirement + TFT 0.31 W / 3.3 V
0.594 A expected; 0.800 A LDO rating
5V_USB
2 × MAX98357A at 1.8 W/8 Ω/92% plus 0.500 A ESP32 source reserve
1.283 A expected; 1.5 A existing net limit
The display no longer adds load to 5V_USB. The user has empirically validated USB power through the socketed dev board in the intended prototype configuration. This empirical validation does not replace the documented current values or establish a new peak-current limit; retain the existing 1.283 A expected 5 V demand and 1.5 A net limit pending measured peak-current evidence.
intentionally unconnected and available; no source-defined assignment changed
Controls — superseded by final mapping below
3, 13, 18, 19, 20, 21, 22
Historical pre-GPIO15 control record; do not use for firmware configuration
I2S BCLK/LRCLK/DIN
4 / 11 / 23
I2S_BCLK/LRCLK/DIN
The firmware source mapping is preserved. No resistive-touch wiring, transaction sequencing, controller selection, or touch firmware support is required.
Resolved interfaces and constraints
Waveshare ESP32-C6-DEV-KIT-N8 uses two 1×16, 2.54 mm headers; carrier J1/J2 are matching female sockets. Preserve the ESP32 module antenna keepout in any later PCB layout.
Each MAX98357A is a socketed I2S amplifier with 0.1 µF and 10 µF bypassing. Each speaker terminal is differential S+/S− only—not headphone, line-level, or ground-referenced.
Speakers are to be PCB-mounted and the educational product has no enclosure. Their specific diameter, depth, pin spacing, and mounting-hole pattern remain required before board placement.
All fitted gameplay controls are normally open to GND and use firmware internal pull-ups. The carrier reset switch was removed; the socketed DevKit retains its own reset function.
Remaining unsupported physical parameters: PCB-mounted speaker diameter, depth, pin spacing, and mounting-hole pattern; display-hole manufacturing tolerances; and a manufacturer-stated display peak/maximum current. Confirm the speaker data and measured display peak current before PCB layout or manufacturing.
Speaker sourcing status — placement blocked
No Flux-library speaker satisfies the approved ~40 mm, 8 Ω, ~2 W requirement. The closest fully documented near-match investigated is Same Sky (formerly CUI Devices) CMS-40288N: 8 Ω, 2 W nominal / 3 W maximum, 40.0 × 28.2 × 11.8 mm body, four plain Ø3 mm mounting holes on a 22.5 × 34 mm center pattern, and solder terminals. Its manufacturer drawing does not dimension the terminal-to-terminal spacing, terminal-hole size, or a recommended PCB land pattern. Therefore it cannot be instantiated or used to replace J3/J4 without inventing electrical footprint geometry, which is expressly disallowed for this project. The official product page is Same Sky CMS-40288N; the drawing mirror reviewed is CMS-40288N datasheet.
Other investigated candidates either lacked a terminal/mounting pattern or were not the required power class: PUI AS04008MR-2-LWC80 is 40 mm, 8 Ω, 2 W but uses lead wires and specifies neither a PCB terminal pattern nor mounting holes; XHXDZ 40MM-8Ω2W provides 40 mm, 8 Ω and 2 W ratings but no authoritative terminal/mounting geometry. A manufacturer mechanical drawing/CAD model that specifies CMS-40288N terminals, or user approval to retain a separate documented two-pin wire connector while using the CMS-40288N only as a mechanically mounted speaker, is required before the full placement can proceed.
Approved QUARKZMAN wired speakers — connector integration hold
The approved replacement is Amazon Italy ASIN B0DB1WM4QR, the QUARKZMAN 2-piece mini speaker listing. The listing states 44 × 31 × 15 mm, 4 Ω, 3 W rated power, a JST-PH2.0 interface, and 100 mm wire length. It describes a wire-terminated speaker and provides no PCB-mount terminal pattern, mounting hole pattern, or retention feature; it must therefore be retained mechanically off-board and interfaced by a mating PCB connector, not represented by an invented speaker footprint. The listing states no separate maximum-power rating.
The verified board-side mating family is JST PH: B2B-PH-K-S(LF)(SN), a 2-position vertical/top-entry, 2.00 mm pitch through-hole header mating with a PHR-2 housing and SPH-002T-P0.5S crimp terminals. JST specifies 2.00 ± 0.05 mm hole pitch, Ø0.7 mm +0.1/0 holes, 4.5 mm header width, approximately 8 mm mounted height, and 2 A AC/DC with AWG24. This is adequate for the 3 W / 4 Ω speaker current (0.87 A RMS). Sources: JST PH catalog and Flux library search.
Polarity verified — authoritative project field evidence: for both speakers, JST pin 1 is SPK+ and JST pin 2 is SPK−. This is field-verified by outward cone movement when a +1.5 V pulse is applied to JST pin 1. J3 P1 is therefore L_SPK+ / U2 S+ and J3 P2 is L_SPK- / U2 S−; J4 P1 is R_SPK+ / U3 S+ and J4 P2 is R_SPK- / U3 S−. Neither BTL amplifier output is connected to ground. The board currently uses 5.00 mm terminal blocks and requires a documented adapter or a future JST-PH footprint change for direct harness mating.
Placement evidence holds
The TFT module dimensions and 44.00 × 76.08 mm mounting-hole center pattern are known, but the source reviewed does not establish the hole-pattern datum relative to the 1×14 header/socket. No TFT mounting holes may be placed from these dimensions alone.
ESP32-C6-WROOM-1 uses a 6 mm × 18 mm PCB antenna-area/keepout at the antenna end. The dev-kit user guide does not provide its board-level datum or USB-C end coordinate; use the existing DevKit footprint orientation and preserve the antenna end clear of carrier copper/components. Sources: Espressif WROOM-1 datasheet and DevKitC-1 user guide.
Historical superseded GPIO14 console plan — do not implement (2026-08-26)
The confirmed mechanical target is now a 180 × 100 mm, Standard 4 Layer carrier. The requested front panel is a landscape MSP2807/TFT at user top-left coordinate (44.5, 6.1) mm, a 5D joystick module at (10.1, 19.8) mm, and one separate START button centered below the TFT. The rear is reserved for left/right Quarkzman 44 × 31 × 15 mm speaker envelopes, their historical pre-finalization differential interfaces (now verified Pin 1=SPK+, Pin 2=SPK-), rear audio clusters, and the centered socketed devboard with USB-C accessible at an edge.
Required user-interface map
Table
Joystick module terminal
Function
Required carrier net / ESP32 GPIO
COM
Common
GND
UP
Up
BTN_UP_GPIO3 / GPIO3
DWN
Down
BTN_DOWN_GPIO13 / GPIO13
LET (user label LEFT)
Left
BTN_LEFT_GPIO18 / GPIO18
RHT
Right
BTN_RIGHT_GPIO19 / GPIO19
SET
A
BTN_A_GPIO21 / GPIO21
RST
B
BTN_B_GPIO22 / GPIO22
MID
Select
GPIO20
Separate front tactile
Start, normally open to GND
GPIO14
The researched 5D-family module has an 8-pin, 2.54 mm header in COM→RST order COM, UP, DWN, LET, RHT, MID, SET, RST; the reverse order is the user-supplied RST, SET, MID, RHT, LEFT, DWN, UP, COM. Its exact Flux library part is unavailable, so an 8-pin 2.54 mm socket/header representation is the safe planned carrier interface. The user-specified 23.3 × 21.7 mm envelope is retained as the placement envelope; research found physically similar 5D modules with the same labels but different published outlines, so it is not a verified fabrication footprint.
Blocking incompatibility — do not flash or fabricate as GPIO14 START
The confirmed firmware source change remains required: GPIO20 = SELECT (joystick MID) and GPIO14 = START (separate tactile). However, the fitted ESP32-C6-DevKitC-1-N8 exposes no GPIO14 on either 1×16 header. The official header list exposes GPIO0–13 (selected), GPIO15, GPIO18–23, TXD0/RXD0, power, ground, and reset, but not GPIO14. Therefore a separate GPIO14 START button cannot be electrically connected through the existing J1/J2 socketed-devboard carrier without an unsupported rework/tap or a devboard change. No GPIO substitution, hidden wire, or GPIO14-only component has been made.
Required resolution before completing the console-revision schematic: either (1) approve an accessible replacement GPIO and matching firmware assignment for START, or (2) specify an electrically documented way to bring GPIO14 out of the selected socketed devboard. Until then, the old discrete controls must remain electrically intact and no replacement joystick/start wiring is safe to commit.
Remaining already-known hold: the TFT mounting-hole datum relative to J5 remains undocumented; no J5 mounting holes may be fabricated from the known center pattern alone. Speaker-harness polarity is field-verified: for both speakers, JST pin 1=SPK+ and JST pin 2=SPK- by outward cone movement with +1.5 V on pin 1. No traces are to be routed in this revision.
Final console controls and 3D preview — superseding record (2026-08-26)
This section supersedes the prior 8-pin joystick-breakout and GPIO14 START proposal. The breakout/header is not used. The controls are now one bare on-PCB 5-way switch for directional input plus four independent front tact switches.
Implemented control parts and GPIO map
Table
Control
Hardware
Carrier net
MCU connection
Electrical rule
UP
S1 D terminal
BTN_UP_GPIO3
GPIO3 / J1 Pin 13
NO to S1 common/GND
DOWN
S1 C terminal
BTN_DOWN_GPIO13
GPIO13 / J2 Pin 3
NO to S1 common/GND
LEFT
S1 B terminal
BTN_LEFT_GPIO18
GPIO18 / J2 Pin 10
NO to S1 common/GND
RIGHT
S1 A terminal
BTN_RIGHT_GPIO19
GPIO19 / J2 Pin 9
NO to S1 common/GND
A
SW6
BTN_A_GPIO21
GPIO21 / J2 Pin 7
NO to GND
B
SW7
BTN_B_GPIO22
GPIO22 / J2 Pin 6
NO to GND
SELECT
SW5
BTN_SELECT_GPIO20
GPIO20 / J2 Pin 8
NO to GND
START
SW9
BTN_START_GPIO15
GPIO15 / J2 Pin 4
NO to GND; ESP32 internal pull-up only
S1 is the Flux-library 504, sourced as the through-hole ALPS SKQUCAA010 4-direction-with-center-push switch. The ALPS drawing identifies A/B/C/D, common, and center terminals; its circuit orientation was used as D=UP, C=DOWN, B=LEFT, A=RIGHT. S1 common is grounded and its center push is intentionally marked no-connect. The datasheet documents a 10 mm square switch family, 50 mA at 12 VDC maximum, and the snap-in 4-direction-plus-center PCB hole pattern; this is a bare component, not a breakout.
Firmware change required before flashing: set SELECT=GPIO20 and START=GPIO15. GPIO15 is an ESP32-C6 strapping/on-board-function pin. SW9 has no external pull resistor and relies only on the ESP32 internal pull-up; do not hold START during reset or boot.
Exact component change record: added S1 (504 / ALPS SKQUCAA010-compatible bare joystick) and SW9 (START); removed SW1–SW4 (four former discrete directional switches) and SW8 (carrier reset switch). SW5 was retained but changed from ambiguous START/SELECT to SELECT-only. SW6 and SW7 remain A and B. The socketed DevKit retains its own documented reset function.
Placement and non-routing state
The preview-display centre is at Flux (-2.5, +18.9) mm, derived from the user’s 180 × 100 mm top-left datum and the stated 87.5 × 31.1 mm module centre; it is landscape (86 × 50 mm).
S1 is front-left; SW6/SW7 are right of the display; SW5/SW9 form the centered SELECT/START pair below it.
J1/J2 are rotated to make the socketed-devboard envelope occupy the rear/bottom area; U2/U3 and C1–C5/R1 are clustered on the rear sides. J3/J4 are at the rear board edge and are verified differential Pin 1=SPK+, Pin 2=SPK- interfaces.
No traces were added or routed. Airwires are expected at this placement stage.
3D preview assets and placements
3D Model (build123d)
: documented 86 × 50 × 1.6 mm module and 57.6 × 43.2 mm landscape active-area massing, top side at (-2.5, +18.9, 0) mm.
3D Model (build123d)
: published 8 × 9 × 10 mm body envelope, top side over S1 at (-63.15, +16.05, 0) mm.
3D Model (build123d)
: a socket-derived 25.4 × 41.7 mm non-vendor envelope, bottom side at (0, -28.75, -1.3) mm, X-rotated 180°.
3D Model (build123d)
: verified 44 × 31 × 15 mm envelope, instantiated under the board at (-66, -30, -1.3) mm and (66, -30, -1.3) mm, each X-rotated 180°.
The preview intentionally does not invent TFT mounting-hole/header relation, DevKit vendor-body/USB datum, speaker retention, or internal speaker geometry. Speaker harness polarity is field-verified: for both speakers, JST pin 1=SPK+ and JST pin 2=SPK- from outward cone movement with +1.5 V on pin 1. The TFT model communicates landscape clearance only; do not use it to fabricate TFT mounting holes. The DevKit model is an assembly envelope derived from J1/J2 rather than a claimed manufacturer-exact mechanical model.
Validation snapshot
The final placement review reports zero component-body overlaps, component-outside-board violations, keepout violations, invalid-layer violations, and edge-placement violations. ERC returned no reported control-pin violations; direct net readback confirms every approved control pin on its stated MCU GPIO, S1 center as no-connect, and SW9 only between GPIO15 and GND.
DRC reports 44 airwires, which are expected because routing is explicitly out of scope. The prior J2/J5 overlapping-copper anomaly was cleared by the image-datum-correct J5 orientation and placement; no other placement or copper DRC findings are reported.
J5 uses 3V3/GND and GPIO7/2/6/10/1/0/5 for MOSI/MISO/SCLK/CS/DC/RST/BL, matching the physical-build header. The backlight is wired active-high.
Direction and A/B controls
PASS
S1 and SW6/SW7 connect to GPIO3/13/18/19/21/22 exactly as configured.
START/SELECT
USER-APPROVED DEVIATION
Hardware is separate START on GPIO15 and SELECT on GPIO20, rather than the current header’s default START=20 and SELECT alias. Before flashing, make the effective firmware values PRG32_PIN_BTN_START=15, separate-SELECT enabled, and PRG32_PIN_BTN_SELECT=20.
Buzzer
PASS / USER-APPROVED OMIT
The current header already sets the buzzer pin to -1; no buzzer is fitted.
Optional setup
USER-APPROVED OMIT
GPIO14 setup is not implemented in the final front control set. Ensure the effective firmware setup pin is disabled (-1) rather than polling an unimplemented input.
On-board RGB
CORRECTED
The physical-build header assigns the on-board RGB LED to GPIO8. The carrier adds no external GPIO8 load; net label was corrected from GPIO8_DISABLED to GPIO8_RGB_LED. The hardware-reference prose conflicts on LCD D/C, but the header and J5 wiring both use GPIO1 for D/C.
Stereo I2S
PASS
GPIO4/11/23 fan out to both MAX98357 boards. U2 SD is directly at 3V3 for left selection; U3 SD is pulled to 3V3 through R1=210 kΩ and the IC’s internal 100 kΩ pulldown, giving the right-channel SD/MODE range.
Speaker load
PASS
The Quarkzman listing specifies 4 Ω / 3 W, within the 4–8 Ω documented speaker range. Both J3/J4 remain BTL differential S+/S− interfaces and neither lead is ground.
The bare ALPS-style directional switch replaces the reference document’s generic digital joystick module by deliberate user approval. Stereo audio is supported by the repository hardware reference and is implemented with two channel-selected MAX98357 boards; it is not a functional conflict with the mono baseline.
Exact speaker-harness polarity research
The exact approved product, Amazon Italy ASIN B0DB1WM4QR, states JST-PH2.0, 100 mm lead length, 4 Ω, and 3 W but provides no vendor wire-color legend or circuit-number mapping. Project field evidence supersedes that listing gap: both speakers move outward with +1.5 V applied to JST pin 1. Therefore J3 P1=L_SPK+/U2 S+, J3 P2=L_SPK-/U2 S−, J4 P1=R_SPK+/U3 S+, and J4 P2=R_SPK-/U3 S−. The 3D speaker models are annotated accordingly.
Recorded field procedure: a brief +1.5 V pulse applied to JST pin 1 drove the cone outward on both supplied speakers. The corresponding marked lead is therefore connected to MAX98357 S+ on both channels for in-phase operation. If the harness is replaced, repeat this test; a continuity test alone identifies the leads but cannot establish acoustic polarity. Do not use the MAX98357 outputs as a ground-referenced load during this check.
J3/J4 are currently 5.00 mm terminal blocks, not JST-PH mating headers; therefore they do not directly mate with the supplied harness. Retaining them is acceptable only as a temporary verified-polarity adapter interface. A production release needs a matching JST-PH header footprint or a documented adapter harness.
3D preview readback
Readback confirms board-level model nodes exist for MSP2807 Landscape Display, Bare 5-Way Joystick, ESP32-C6 DevKit Socket Envelope, and left/right Quarkzman Speaker Envelope. The preview assets remain at their documented landscape/front or rear/bottom placements with unit scale: TFT top-side landscape at (-2.5, +18.9, 0) mm; joystick top-side at (-63.15, +16.05, 0) mm; DevKit socket envelope bottom-side at (0, -28.75, -1.3) mm with 180° X rotation; speaker envelopes bottom-side at (-66, -30, -1.3) mm and (66, -30, -1.3) mm with 180° X rotation. Speaker envelope annotations identify verified Pin 1 positive polarity on both left and right harnesses; the common bottom-side envelope orientation is retained for consistent in-phase stereo assembly.
Current release blockers
Apply the explicit GPIO15 START / GPIO20 separate SELECT / disabled setup firmware configuration before flashing.
Choose a direct JST-PH board interface or qualified adapter for manufacture; the field-verified harness polarity is now documented.
Obtain the TFT header-to-mounting-hole datum before adding fabricable TFT mounting holes.
Route the 44 expected airwires in a later routing phase and complete normal post-route DRC before fabrication.
Result: corrected. The user-supplied front photograph establishes the exact landscape datum: the 1×14 through-hole header runs down the left short edge, and the J2/pin-1 end is at the top-left. Before correction, J5 was top-side at rotation 90° and its pads formed a horizontal row, which would not accept the photographed module without a 90° orientation error.
J5 is now top-side at (-45.5, +43.9) mm, rotation 0°. Its square Pin 1 pad is at the top-left; pads 2 through 14 descend the left edge at 2.54 mm pitch. The established electrical order is unchanged and verified: VCC, GND, CS, RESET, DC/RS, MOSI, SCK, LED, MISO, then the five deliberately unconnected touch pins. The J5 3D socket model is unit-scale and unrotated relative to the corrected footprint.
The landscape display preview remains centered at (-2.5, +18.9) mm and was refreshed to show the left-edge vertical header plus a top-left pin-1 marker. This representation records the photo-derived header orientation only; it does not invent a TFT mounting-hole datum. ERC reports no added electrical issue, placement DRC reports no overlap/out-of-bounds/keepout/invalid-layer issue, and only the 44 intentional pre-route airwires remain.
The validated msp2807-landscape-preview.build123d asset is now attached as the J5 MSP2807 Landscape Display model node, a child of the J5 element rather than a detached board-level preview. Its local position is (43, -25, 0) mm, rotation is 0 0 0, scale is 1, Z is up, and it inherits J5’s top-side placement and 0° orientation. This local offset aligns the asset’s 86 × 50 mm board centre to the front-centred display position while its left-edge header and top-left pin-1 region follow J5.
Scene readback confirms the new model is parented under J5 and the prior detached MSP2807 Landscape Display node is disabled to prevent a duplicate render. The asset resolves to the validated project storage object, with physical materials and model edges enabled. No J5 electrical pin, net, or placement rotation changed during attachment; J5 still has square Pin 1 at the physical top-left and pads 2–14 descending the left edge. J5-specific mechanical/ERC checks report no violation; only the intentional board-wide airwires remain pending routing.
Rear audio symmetry and preview verification — 2026-08-26
The symmetry check used the actual footprint body rectangles, not the offset component origins. Both MAX98357A bodies are 18.0848 × 21.2024 mm and are on Bottom with parent rotation 180°. After applying those footprint-local offsets:
Table
Module
Body X extents (mm)
Body centre (mm)
Body Y extents (mm)
Rear model state
U2 left
-37.9324 to -19.8476
(-28.8900, -32.6012)
-43.2024 to -22.0000
3006 MAX98357 model, local z=0.3 mm, scale 1
U3 right
19.8476 to 37.9324
(+28.8900, -32.6012)
-43.2024 to -22.0000
same model, local z=0.3 mm, scale 1
The body centres are exact reflections about x=0 at the same Y; no position adjustment was needed. The apparent component origins (U2=-20.00 mm, U3=+37.78 mm) are intentionally not mirror values because the breakout footprint origin is offset from its body. Both attached models inherit the same bottom-side 180° parent orientation, have scale 1 and Z-up, and point to the same 3006-MAX98357 STEP asset.
The rear preview was refreshed with the Rear audio model visibility selector ruleset: U2/U3 models use physical materials and visible edges without changing any audio nets, scale, position, or rotation. Readback confirms the centered DevKit socket envelope and the left/right speaker envelopes remain in the rear assembly. Relevant mechanical DRCs report no component-body overlap, outside-board, keepout, invalid-layer, edge-placement, or overlapping-copper violation; the remaining 44 airwires are intentional until routing.
A five-line bottom-silkscreen instruction block was added at x=22.5 mm, y=35.0/33.5/32.0/30.5/29.0 mm, horizontal 0° orientation, with a 1.0 mm title and 0.8 mm minimum-height instructions. After the verified test, its durable field record is:
Text
SPEAKER POLARITY TEST
1) PIN 1=SPK+ / PIN 2=SPK-
2) USE 1.5V CELL: + to JST pin 1
3) MARK CONE OUT = SPK+
MATCH L/R PINOUT - DO NOT GUESS WIRE COLORS
The block is on Bottom Silkscreen between the y=25 mm and y=40 mm via rows, clear of the rear DevKit sockets, U2/U3 bodies, J3/J4, speaker envelopes, capacitor cluster, pads, and board edge. It records the verified assignment without inferring wire colors: Pin 1 is SPK+ and Pin 2 is SPK- for both in-phase channels. No lead is ground-referenced.
The user’s 1.5 V outward-cone test is authoritative for this project. Final schematic assignment: J3:P1 → L_SPK+ → U2:S+, J3:P2 → L_SPK- → U2:S-, J4:P1 → R_SPK+ → U3:S+, and J4:P2 → R_SPK- → U3:S-. The net labels, J3/J4 role details, rear silkscreen, test block, and speaker-envelope annotations have been updated. This retains the BTL differential outputs and establishes consistent left/right in-phase convention; neither speaker lead is connected to GND.
Bottom-side image and geometry review confirmed the five text nodes form one aligned readable block. Mechanical DRC remains free of overlap/out-of-bounds/keepout/invalid-layer/edge-placement/overlapping-copper findings; only the 44 intentional pre-route airwires remain.
Scope and locked architecture
Confirmed display socket
Voltage choice and power budget
Firmware-authoritative GPIO mapping
Resolved interfaces and constraints
Evidence and remaining limits
Speaker sourcing status — placement blocked
Approved QUARKZMAN wired speakers — connector integration hold
Placement evidence holds
Historical superseded GPIO14 console plan — do not implement (2026-08-26)
Required user-interface map
Blocking incompatibility — do not flash or fabricate as GPIO14 START
Final console controls and 3D preview — superseding record (2026-08-26)