U3 iCE40UP5K-SG48I FPGA: place at the center of the PCB.

ADC interface: route/locate to the left side of the FPGA.

USB interface: route/locate to the right side of the FPGA.

C8 100nF FPGA core decoupling capacitor: place electrically close to U3 VCORE/VCC pins on the +1V2_FPGA rail.

C9 100nF FPGA 3.3V IO decoupling capacitor: place electrically close to U3 VCCIO pins on the +3V3_MAIN rail.

C10 4.7uF FPGA local bulk decoupling capacitor: place electrically close to U3 VCCIO pins on the +3V3_MAIN rail.

U4 W25Q32JVSSIQ SPI configuration flash: place near the FPGA top side for short configuration-SPI connections.

C11 100nF SPI flash decoupling capacitor: place electrically close to U4 VCC on the +3V3_MAIN rail.

U4 W25Q32JVSSIQ SPI configuration flash: keep near the FPGA for short SPI_CS, SPI_CLK, SPI_MOSI, and SPI_MISO configuration traces.

SW1 FPGA reset/program pushbutton: place near a board edge for user access while keeping FPGA_RESET_B routing short and away from noisy switching nodes.

D2 blue FPGA firmware status LED: place near a board edge for clear visibility; keep R3 close to D2 or along the short route from U3 GPIO IOB_6a to the LED.

D4 green system power/status LED: place near a PCB edge so it is visible during hardware debugging and bring-up.

R38 1kΩ system status LED current-limit resistor: place close to D4 or inline with the short +3V3_MAIN -> R38 -> SYS_STATUS_LED -> D4 path.

SYS_STATUS_LED routing: keep the LED circuitry away from RF signal paths, RF/LO traces, the PLL loop filter, and sensitive ADC/IF analog routing to avoid interference.

D5 blue FPGA configuration/activity status LED: place near a PCB edge so it is clearly visible during FPGA configuration and activity debugging.

R39 1kΩ FPGA_STATUS_LED current-limit resistor: place close to D5 or inline with the short U3:IOT_45a_G1 -> R39 -> FPGA_STATUS_LED -> D5 path.

FPGA_STATUS_LED routing: keep this LED circuitry away from RF signal paths, RF/LO traces, the PLL loop filter, and sensitive ADC/IF analog routing to avoid coupling activity noise into the RF acquisition chain.

J2 USB4215-03-A USB Type-C connector: place on the right board edge for FPGA programming/debug and future USB 2.0 data access.

C12 100nF USB_5V decoupling capacitor: place electrically close to J2 VBUS pins and connect with a short return to GND.

D3 USBLC6-2SC6 USB differential-line ESD protection diode array: place very close to USB connector J2, before the USB_DP/USB_DN pair continues toward U5, so the transient is shunted at the connector entry point.

C27 100nF local ESD protection decoupling capacitor: place close to D3 on +3V3_MAIN with a short, low-impedance return to GND.

USB differential routing: keep USB_DP and USB_DN from J2 through D3 short, symmetric, tightly coupled, and length-balanced before continuing to U5; avoid stubs and noisy switching areas.

R4 5.1kΩ USB Type-C CC1 pull-down resistor: place electrically close to J2 CC1 pin to support the Type-C sink/device configuration.

R5 5.1kΩ USB Type-C CC2 pull-down resistor: place electrically close to J2 CC2 pin to support the Type-C sink/device configuration.

U5 FT2232H LQFP-64 USB FIFO bridge: place between FPGA U3 and USB connector J2, with USB_DP/USB_DN facing J2 and FIFO-side pins oriented toward U3 for a later connection stage.

C13 100nF FT2232H decoupling capacitor: place electrically close to U5 3.3V power pins on +3V3_MAIN with a short return to GND.

Y1 12 MHz FT2232H reference crystal: place electrically close to U5 OSCI/OSCO clock pins with very short, symmetric traces and keep away from noisy switching nodes.

C14 18pF FT2232H crystal load capacitor: place electrically close to U5 OSCI / FT_CLK1 and Y1, with a short direct return to GND to minimize clock noise and startup risk.

C15 18pF FT2232H second crystal load capacitor: place electrically close to U5 OSCO / FT_CLK2 and Y1, with a short direct return to GND to minimize clock noise and startup risk.

R6 1MΩ FT2232H crystal oscillator feedback resistor: place electrically close to Y1 and U5 OSCI/OSCO clock pins, spanning FT_CLK1 to FT_CLK2 with a very short loop.

R7 33Ω FIFO clock series termination resistor: place electrically close to U5 FT2232H CLKOUT output pin to damp clock edge ringing before the trace runs toward U3.

TP1 FIFO_CLK SMD test point: place near the FPGA edge for convenient debug probing while keeping the stub short.

R8 33Ω FIFO_D0 series termination resistor: place electrically close to U5 FT2232H ADBUS0 pin to damp FIFO data edge ringing before the trace runs toward U3.

TP2 FIFO_D0 SMD test point: place in an accessible debug location while keeping the probe stub short.

R9 33Ω FIFO_D1 series termination resistor: place electrically close to U5 FT2232H ADBUS1 pin to damp FIFO data edge ringing before the trace runs toward U3.

TP3 FIFO_D1 SMD test point: place in an accessible debug location while keeping the probe stub short.

R10 33Ω FIFO_WR series termination resistor: place electrically close to U5 FT2232H WR# / ACBUS3 pin to damp FIFO write-control edge ringing before the trace runs toward U3.

TP4 FIFO_WR SMD test point: position in an accessible debug location for FIFO write probing while keeping the probe stub short.

R11 33Ω FIFO_TXE_N series termination resistor: place electrically close to U5 FT2232H TXE# / ACBUS1 pin to damp FIFO status edge ringing before the trace runs toward U3.

TP5 FIFO_TXE_N SMD test point: position in an accessible debug location for FIFO ready/status probing while keeping the probe stub short.

U6 AD9280ARSZRL ADC: place between the future RF section and FPGA U3, with analog input oriented toward the RF side and digital output pins facing toward the FPGA.

C16 100nF ADC local decoupling capacitor: place electrically close to U6 AVDD/DRVDD on +3V3_MAIN with a short return to GND.

C17 10uF ADC local bulk decoupling capacitor: place electrically close to U6 AVDD/DRVDD power pins on +3V3_MAIN, prioritizing the shortest practical supply and ground return paths for bulk charge support.

C18 100nF ADC high-frequency decoupling capacitor: place closest to U6 AVDD/DRVDD power pins on +3V3_MAIN, prioritizing the shortest possible decoupling loop to GND for high-frequency noise suppression.

FB3 600Ω @ 100MHz ADC analog supply ferrite bead: place very close to U6 AD9280 AVDD so +3V3_MAIN is locally filtered into +3V3_ADC for the ADC analog supply; keep this bead and filtered analog rail isolated from FPGA, FIFO, USB, LO/SPI, switching regulators, and other digital switching regions.

C30 10uF ADC analog supply bulk filtering capacitor: place on +3V3_ADC immediately adjacent to U6 AVDD and FB3:P2, with a short, low-impedance return to GND; minimize the +3V3_ADC loop area and avoid sharing this filtered analog node with noisy digital loads.

ADC analog supply routing: keep FB3 -> +3V3_ADC -> U6 AVDD and C30 compact, quiet, and separated from RF/IF analog traces and high-edge-rate digital clock/data routing.

R12 33Ω ADC_D0 series termination resistor: place electrically close to U6 AD9280 D0 output pin to damp edge ringing before the trace runs toward FPGA U3.

TP6 ADC_D0 SMD test point: position in an accessible debug location for ADC data probing while keeping the probe stub short.

R13 33Ω ADC_D1 series termination resistor: place electrically close to U6 AD9280 D1 output pin to damp edge ringing before the trace runs toward FPGA U3.

TP7 ADC_D1 SMD test point: position in an accessible debug location for ADC data probing while keeping the probe stub short.

R14 33Ω ADC_CLK series termination resistor: place electrically close to the selected U3 FPGA clock-capable GPIO output pin (U3:IOT_46b_G0) before the clock trace runs toward ADC U6.

TP8 ADC_CLK SMD test point: position in an accessible debug location while keeping the probe stub very short; ADC_CLK routing must be extremely short, clean, and isolated from noisy switching nodes.

J3 SMA edge-mount 50Ω RF input connector: place on the left PCB edge so the RF input launches directly into the board with a short, linear, and clean RF path.

C19 100pF RF ceramic AC-coupling capacitor: place immediately after J3 in the RF path, keeping RF_IN and RF_AC traces short and straight with a solid nearby GND return.

U7 SPF5189Z SOT-89 LNA: place immediately after C19 in the RF path, with RF_AC entering the LNA input and the combined RF output/DC-bias node on LNA_VCC_FILTERED. Keep the J3 -> C19 -> U7 path short, straight, and linear with solid nearby ground return.

C20 100nF LNA power decoupling capacitor: place electrically close to the +5V_MAIN side of the LNA bias feed with a very short return to GND.

L1 68nH RF bias choke: place close to U7 pin 3 / LNA_VCC_FILTERED bias node, with L1:P2 tight to the U7 combined RF output/DC-bias pin and L1:P1 fed from +5V_MAIN.

C21 10uF LNA bulk supply filtering capacitor: place close to the same LNA_VCC_FILTERED bias node as U7 pin 3 and L1:P2, with a short, low-impedance return to GND.

LNA bias feed: keep the +5V_MAIN -> L1 -> LNA_VCC_FILTERED bias path physically isolated from the J3 -> C19 -> U7 RF input path; keep RF traces short, linear, and uninterrupted.

U8 SA612A RF mixer: place directly after U7 SPF5189Z LNA to maintain a linear RF chain; the current schematic uses LNA_VCC_FILTERED as the U7 combined RF output/DC-bias node feeding U8 IN_A, with LO_IN and IF_OUT left as standalone interface nets for later LO source and IF processing stages.

C22 100nF mixer decoupling capacitor: place electrically close to U8 VCC on +5V_MAIN with a short direct return to GND.

FB2 600Ω @ 100MHz mixer RF supply ferrite bead: place very close to U8 mixer supply pins so +5V_MAIN is filtered locally into +5V_MIXER_RF for the mixer stage; keep FB2 and the filtered mixer supply physically isolated from FPGA, FIFO, USB, ADC digital clock/data, switching regulators, and other digital switching regions.

C29 10uF mixer RF supply bulk filtering capacitor: place on +5V_MIXER_RF immediately adjacent to U8 VCC and FB2:P2, with a short, low-impedance return to GND; minimize the +5V_MIXER_RF loop area and avoid sharing this local filtered node with noisy digital loads.

C23 100pF RF ceramic IF AC-coupling capacitor: place very close to U6 AD9280 AIN / IF_ADC input, between U8 IF_OUT and IF_ADC, keeping the IF trace short and isolated from FPGA, FIFO, USB, and switching-power digital circuitry.

R15 49.9Ω precision 0603 ADC IF input termination resistor: place immediately at U6 AD9280 AIN / IF_ADC with a shortest-possible return to GND; keep the termination stub minimal and co-located with C23 and the ADC analog input.

IF_ADC routing: route as a short, isolated analog IF connection from C23 to U6 AIN and R15, avoiding digital clock/data routes and noisy supply nodes.

U9 ADF4351 RF local oscillator synthesizer: place near U8 mixer LO input so LO_RF_OUT / LO_IN routing is very short; isolate LO traces from FPGA, FIFO, USB, ADC clock/data, and other digital circuitry. -- C24 100nF LO synthesizer decoupling capacitor: existing local decoupling component; preserve its schematic connection while the new FB1/C28 filtered +3V3_RF rail provides ADF4351 bulk RF supply filtering.

FB1 600Ω @ 100MHz ADF4351 RF supply ferrite bead: place very close to U9 ADF4351 supply pins so +3V3_MAIN is filtered into +3V3_RF locally at the synthesizer; keep the bead and filtered RF rail physically isolated from switching regulators, FPGA/FIFO/USB digital routing, and other digital switching regions.

C28 10uF ADF4351 RF supply bulk filtering capacitor: place on +3V3_RF immediately adjacent to U9 power pins and FB1:P2, with a short, low-impedance return to GND; minimize the +3V3_RF loop area and avoid sharing this local filtered node with noisy digital loads.

R16 4.7kΩ ADF4351 PLL loop filter resistor: place extremely close to U9 CPOUT / charge-pump pin, keeping the connection from U9:CPOUT to R16:P1 as short and quiet as possible.

C25 10nF ADF4351 PLL loop filter capacitor: place immediately adjacent to R16 and U9 CPOUT with a shortest-possible return to GND; keep PLL_FILTER_1 isolated from FPGA, FIFO, USB, ADC clock/data, SPI, and other digital traces.

R17 1kΩ ADF4351 secondary PLL loop filter resistor: place extremely close to U9 VTUNE and the R16/C25 charge-pump filter area, keeping PLL_FILTER_1 to PLL_FILTER_2 short, quiet, and isolated from switching regulators and digital routing.

C26 100nF ADF4351 secondary PLL loop filter capacitor: place immediately at the U9 VTUNE / PLL_FILTER_2 node with a shortest-possible GND return; keep the PLL_FILTER_2 node isolated from FPGA, FIFO, USB, ADC clock/data, SPI, switching regulators, and other noisy routing.

ADF4351 PLL loop filter group: keep R16, C25, R17, C26, PLL_FILTER_1, and PLL_FILTER_2 clustered tightly at U9 CPOUT/VTUNE, with guard/ground-aware layout and no digital or switching-power traces crossing the loop filter area.

R18 33Ω ADF4351 SPI clock series termination resistor: place close to the selected FPGA U3 output pin (U3:IOB_22a) before the LO_SPI_CLK trace runs toward U9 CLK, minimizing the source-to-resistor path length.

R19 33Ω ADF4351 SPI data series termination resistor: place close to the selected FPGA U3 output pin (U3:IOB_24a) before the LO_SPI_DATA trace runs toward U9 DATA, minimizing the source-to-resistor path length.

ADF4351 SPI routing: route LO_SPI_CLK and LO_SPI_DATA away from RF-sensitive areas including the J3/C19/U7/U8 RF chain, U8 LO input, U9 RF output/LO_IN path, and the ADF4351 PLL loop filter nodes; keep these digital traces short with a continuous ground reference.

R21 33Ω ADC_D2 series termination resistor: place electrically close to U6 AD9280 D2 output pin to damp edge ringing before the trace runs toward FPGA U3.

TP10 ADC_D2 SMD test point: position in an accessible debug location while keeping the probe stub short.

ADC parallel bus routing: maintain ADC_D0, ADC_D1, and ADC_D2 as an ordered, parallel bus from U6 toward U3, keeping the signal path clean and preserving spacing/length consistency where practical.

R22 33Ω ADC_D3 series termination resistor: place electrically close to U6 AD9280 D3 output pin to damp edge ringing before the trace runs toward FPGA U3.

TP11 ADC_D3 SMD test point: position in an accessible debug location while keeping the probe stub short.

ADC parallel bus routing: maintain ADC_D0, ADC_D1, ADC_D2, and ADC_D3 as an ordered, parallel bus from U6 toward U3, using U3:IOB_29b adjacent to U3:IOB_31b for ADC_D3 where practical and preserving spacing/length consistency.

R23 33Ω ADC_D4 series termination resistor: place electrically close to U6 AD9280 D4 output pin to damp edge ringing before the trace runs toward FPGA U3.

TP12 ADC_D4 SMD test point: position in an accessible debug location while keeping the probe stub short.

ADC parallel bus routing: maintain ADC_D0, ADC_D1, ADC_D2, ADC_D3, and ADC_D4 as an ordered, parallel bus from U6 toward U3. Use the selected nearby available FPGA GPIO U3:IOT_37a for ADC_D4 while preserving spacing/length consistency toward the FPGA where practical.

R24 33Ω ADC_D5 series termination resistor: place electrically close to U6 AD9280 D5 output pin to damp edge ringing before the trace runs toward FPGA U3.

TP13 ADC_D5 SMD test point: position in an accessible debug location while keeping the probe stub short.

ADC parallel bus routing: maintain ADC_D0, ADC_D1, ADC_D2, ADC_D3, ADC_D4, and ADC_D5 as an ordered, parallel bus from U6 toward U3. Use the selected adjacent FPGA GPIO U3:IOT_36b next to U3:IOT_37a for ADC_D5 where practical and preserve spacing/length consistency.

R25 33Ω ADC_D6 series termination resistor: place electrically close to U6 AD9280 D6 output pin to damp edge ringing before the trace runs toward FPGA U3.

TP14 ADC_D6 SMD test point: position in an accessible debug location while keeping the probe stub short.

ADC parallel bus routing: maintain ADC_D0, ADC_D1, ADC_D2, ADC_D3, ADC_D4, ADC_D5, and ADC_D6 as an ordered, parallel bus from U6 toward U3. Use the selected adjacent FPGA GPIO U3:IOT_39a next to U3:IOT_36b for ADC_D6 where practical and preserve spacing/length consistency.

R26 33Ω ADC_D7 series termination resistor: place electrically close to U6 AD9280 D7 output pin to damp edge ringing before the trace runs toward FPGA U3.

TP15 ADC_D7 SMD test point: position in an accessible debug location while keeping the probe stub short.

ADC parallel bus routing: maintain ADC_D0 through ADC_D7 as an ordered, parallel bus from U6 toward U3. Use the selected adjacent FPGA GPIO U3:IOT_38b next to U3:IOT_39a for ADC_D7 where practical and preserve spacing/length consistency.

R27 33Ω ADC_SYNC series termination resistor: place electrically close to the selected FPGA synchronization GPIO U3:IOT_41a, minimizing the source-to-resistor path before ADC_SYNC runs toward U6.

TP16 ADC_SYNC SMD test point: position in an accessible debug location while keeping the probe stub short.

ADC_SYNC routing: keep the synchronization/control timing route from R27 to U6:CLAMP short, clean, and adjacent to the ordered ADC bus where practical, avoiding noisy switching and RF-sensitive areas.

R28 33Ω FIFO_D2 series termination resistor: place electrically close to U5 FT2232H ADBUS2 pin to damp FIFO data edge ringing before the trace runs toward FPGA U3.

TP17 FIFO_D2 SMD test point: position in an accessible debug location while keeping the probe stub short.

FIFO parallel bus routing: maintain FIFO_D0, FIFO_D1, and FIFO_D2 as an ordered, parallel bus from U5 toward U3. Use the selected available FPGA GPIO U3:IOB_5b for FIFO_D2 because the pins immediately adjacent to FIFO_D1 are already allocated; preserve spacing and length consistency where practical.

R29 33Ω FIFO_D3 series termination resistor: place electrically close to U5 FT2232H ADBUS3 pin to damp FIFO data edge ringing before the trace runs toward FPGA U3.

TP18 FIFO_D3 SMD test point: position in an accessible debug location while keeping the probe stub short.

FIFO parallel bus routing: maintain FIFO_D0, FIFO_D1, FIFO_D2, and FIFO_D3 as an ordered, parallel bus from U5 toward U3. Use the selected adjacent FPGA GPIO U3:IOB_0a next to the existing FIFO_D2 GPIO U3:IOB_5b where practical, preserving spacing and length consistency.

R30 33Ω FIFO_D4 series termination resistor: place electrically close to U5 FT2232H ADBUS4 pin to damp FIFO data edge ringing before the trace runs toward FPGA U3.

TP19 FIFO_D4 SMD test point: position in an accessible debug location while keeping the probe stub short.

FIFO parallel bus routing: maintain FIFO_D0, FIFO_D1, FIFO_D2, FIFO_D3, and FIFO_D4 as an ordered, parallel bus from U5 toward U3. Use the selected adjacent FPGA GPIO U3:IOB_2a next to the existing FIFO_D3 GPIO U3:IOB_0a where practical, preserving spacing and length consistency.

R31 33Ω FIFO_D5 series termination resistor: place electrically close to U5 FT2232H ADBUS5 pin to damp FIFO data edge ringing before the trace runs toward FPGA U3.

TP20 FIFO_D5 SMD test point: position in an accessible debug location while keeping the probe stub short.

FIFO parallel bus routing: maintain FIFO_D0, FIFO_D1, FIFO_D2, FIFO_D3, FIFO_D4, and FIFO_D5 as an ordered, parallel bus from U5 toward U3. Use the selected adjacent FPGA GPIO U3:IOB_4a next to the existing FIFO_D4 GPIO U3:IOB_2a where practical, preserving spacing and length consistency.

R32 33Ω FIFO_D6 series termination resistor: place electrically close to U5 FT2232H ADBUS6 pin to damp FIFO data edge ringing before the trace runs toward FPGA U3.

TP21 FIFO_D6 SMD test point: position in an accessible debug location while keeping the probe stub short.

FIFO parallel bus routing: maintain FIFO_D0, FIFO_D1, FIFO_D2, FIFO_D3, FIFO_D4, FIFO_D5, and FIFO_D6 as an ordered, parallel bus from U5 toward U3. Prefer the selected adjacent FPGA GPIO U3:IOB_3b_G6 next to the existing FIFO_D5 GPIO U3:IOB_4a where practical, preserving spacing and length consistency.

R33 33Ω FIFO_D7 series termination resistor: place electrically close to U5 FT2232H ADBUS7 pin to damp FIFO data edge ringing before the trace runs toward FPGA U3.

TP22 FIFO_D7 SMD test point: position in an accessible debug location while keeping the probe stub short.

FIFO parallel bus routing: maintain FIFO_D0 through FIFO_D7 as an ordered, parallel bus from U5 toward U3. Use the selected adjacent FPGA GPIO U3:IOT_49a next to the existing FIFO_D6 GPIO U3:IOB_3b_G6 where practical, preserving spacing and length consistency.

R34 33Ω FIFO_RXF_N receive-status series termination resistor: place electrically close to U5 FT2232H RXF# / ACBUS0 pin to damp FIFO status edge ringing before the trace runs toward FPGA U3.

TP23 FIFO_RXF_N SMD test point: position in an accessible debug location while keeping the probe stub short.

FIFO control routing: keep FIFO_CLK, FIFO_WR, FIFO_TXE_N, and FIFO_RXF_N short, grouped, and routed together where practical between U5 and U3, with series resistors close to U5.

R35 33Ω FIFO_OE_N output-enable series termination resistor: place electrically close to U5 FT2232H OE# / ACBUS4 pin to damp FIFO output-enable edge ringing before the trace runs toward FPGA U3.

TP24 FIFO_OE_N SMD test point: position in an accessible debug location while keeping the probe stub short.

FIFO control routing: keep FIFO_CLK, FIFO_WR, FIFO_TXE_N, FIFO_RXF_N, and FIFO_OE_N short, grouped, and routed together where practical between U5 and U3, with series resistors close to U5.

R36 33Ω FIFO_RD_N read-control series termination resistor: place electrically close to U5 FT2232H RD# / ACBUS2 pin to damp FIFO read-control edge ringing before the trace runs toward FPGA U3.

TP25 FIFO_RD_N SMD test point: position in an accessible debug location while keeping the probe stub short.

FIFO control routing: keep FIFO_CLK, FIFO_WR, FIFO_TXE_N, FIFO_RXF_N, FIFO_OE_N, and FIFO_RD_N short, grouped, and routed together where practical between U5 and U3, with series resistors close to U5.

J4 1x6 SMD FPGA debug/programming header: place near a board edge for easy external access; keep SPI_CLK, SPI_MOSI, SPI_MISO, and FPGA_RESET_B traces short, clean, and grouped from U3/U4 toward the header.

R37 10kΩ FPGA_BOOT_SEL pull-up resistor: place close to the selected U3 boot/config GPIO connection, with a short trace from R37:P2 to U3:IOT_48b and a short connection from R37:P1 to +3V3_MAIN.

FPGA_BOOT_SEL routing: keep this boot-state control trace short, quiet, and away from noisy switching/RF regions; avoid unnecessary stubs.

SW1 system reset pushbutton: place near a PCB edge for easy user access; keep the FPGA_RESET_N path short and avoid RF/LO/PLL/ADC analog regions.

R40 10kΩ FPGA_RESET_N pull-up resistor: place close to the U3 reset/configuration area or along the short reset net path, with a short connection to +3V3_MAIN.

C31 100nF FPGA_RESET_N debounce/filter capacitor: place close to the reset pin/load side with a very short return to GND to minimize reset-line noise susceptibility.

TP26 FPGA_RESET_N SMD test point: place in an accessible debug location while keeping the probe stub short and away from RF-sensitive routing.

FPGA_RESET_N routing: keep reset circuitry away from the RF section and route away from J3/C19/U7/U8/U9, RF/LO traces, PLL loop filter nodes, and ADC IF analog input routing.