Power Entry Stage Design

Thought for 4 sec

flux

Work done

Refined PCB component placement only; no routing was performed.
Floorplanned the SAR board per the constraints file: RF chain left in order J3 → C19 → U7 → U8 → U6, U9 near U8, PLL filter parts beside U9, ADC center-left, FPGA centered, FT2232H/USB on the right, power along the top, and debug/test/LED/reset along the bottom.
Ran a focused cleanup pass to keep the crystal loop and power-entry/debug access from crowding while preserving the routing corridors.

Success criteria review

✅ RF chain ordering and left-side RF isolation corridor are preserved.
✅ PLL filter remains immediately beside U9, with U9 close to U8 for a short LO path.
✅ U6 is center-left and ADC bus series parts are between U6 and U3 for a straight bus channel.
✅ U3 remains centered with bus corridors preserved toward ADC on the left and FIFO/USB on the right.
✅ U5 and J2 are grouped on the right with USB support/ESD nearby.
✅ Power and debug sections are assigned to the top and bottom edges respectively.
✅ Schematic connectivity was not changed and no PCB routing was created.

Next steps

Proceed with staged routing: RF first, then PLL/ADC clock, ADC bus, USB pair, FIFO bus, power, and finally debug/GPIO.

Run placement DRC

Tighten ADC corridor

Check unmet constraints

Export placement report

Refine this doc

Ask about this doc

SAR Receiver PCB Constraints and Layout Specification

Project Overview

Project Type:

Superheterodyne SAR Receiver
Tower-mounted surveillance radar prototype
FPGA-based ADC acquisition
USB streaming interface
Coherent RF local oscillator generation

Primary Goals:

Stable RF reception
Clean ADC acquisition
Reliable FPGA data capture
USB streaming to external SBC
Manufacturable low-cost PCB
Easy routing and debugging

Board Revision:

Rev A

Target Board Size:

70 mm × 50 mm

Target Layer Count:

4 layers

Fabrication Target:

Standard low-cost FR4 fabrication

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PCB STACKUP

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Layer 1:

RF traces
Critical clocks
High-speed digital
Primary component placement

Layer 2:

Solid uninterrupted GND plane
No major splits
Preserve RF return continuity

Layer 3:

Power plane
Secondary routing
Filtered domains

Layer 4:

Secondary signal routing
Debug traces
Low-speed control signals

Board Material:

FR4
1.6 mm thickness
1 oz copper

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FUNCTIONAL ZONES

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LEFT SIDE — RF SECTION Components:

J3 SMA Connector
C19 RF coupling capacitor
U7 LNA
U8 Mixer
U9 ADF4351
PLL filter network

CENTER-LEFT — ADC SECTION Components:

U6 ADC
ADC decoupling
ADC filtering

CENTER — FPGA SECTION Components:

U3 FPGA
FPGA decoupling
SPI flash

RIGHT SIDE — USB SECTION Components:

U5 FT2232H
D3 USB ESD protection
J2 USB connector

TOP EDGE — POWER SECTION Components:

Input protection
Polyfuse
TVS diode
Regulators
Ferrite beads
Bulk capacitors

BOTTOM EDGE — DEBUG SECTION Components:

LEDs
Test points
Reset circuitry
Debug headers

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COMPONENT PLACEMENT COORDINATES

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Table

Component	X Position	Y Position	Rotation
J3 SMA	3 mm	25 mm	0°
C19	8 mm	25 mm	0°
U7 LNA	12 mm	25 mm	0°
U8 Mixer	20 mm	25 mm	0°
U9 ADF4351	18 mm	12 mm	0°
PLL Filter	24 mm	12 mm	0°
U6 ADC	30 mm	25 mm	0°
U3 FPGA	42 mm	25 mm	90°
U5 FT2232H	58 mm	25 mm	0°
J2 USB	67 mm	25 mm	0°
Power Section	35 mm	5 mm	0°
LEDs	35 mm	46 mm	0°
Debug Header	55 mm	46 mm	0°

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FPGA ORIENTATION RULES

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ADC-facing FPGA pins:

Face LEFT
Connect toward ADC

FIFO/USB-facing FPGA pins:

Face RIGHT
Connect toward FT2232H

Clock-sensitive FPGA pins:

Prefer TOP side

Placement Goals:

Straight bus routing
Minimal vias
Minimal crossover
Minimal airwires

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RF ROUTING RULES

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RF Path Order: J3 → C19 → U7 → U8 → U6

RF Trace Rules:

50Ω impedance controlled traces
Keep traces extremely short
Avoid vias if possible
Use grounded copper around RF traces
Avoid digital traces crossing RF section
Preserve continuous return path

LO Routing Rules:

Shortest possible LO route
Isolate from USB and FPGA
No noisy digital traces nearby

PLL Filter Rules:

Place immediately beside ADF4351
Isolated copper region
No switching power traces nearby

Preferred RF Trace Width:

Approximate 50Ω microstrip based on stackup
Use PCB impedance calculator if needed

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ADC ROUTING RULES

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ADC Bus:

ADC_D0 to ADC_D7

Rules:

Route as ordered parallel bus
Similar path lengths
Avoid stubs
Minimize vias
Avoid crossing split planes

ADC Clock:

Highest routing priority after RF
Short direct route
Isolate from USB
Isolate from switching regulators

ADC Trace Width:

0.15 mm minimum
0.20 mm preferred

Allowed Bend Angle:

45° only

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USB ROUTING RULES

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USB Differential Pair:

USB_DP
USB_DN

Rules:

Tight differential pair coupling
Length matched
No stubs
No sharp corners
Avoid RF section

Differential Pair Constraints:

Width: 0.15 mm
Gap: 0.15 mm
Length tolerance: ±0.2 mm

USB ESD Placement:

Directly beside USB connector
Minimal stub length

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FIFO BUS ROUTING RULES

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FIFO Nets:

FIFO_D0 to FIFO_D7
FIFO_CLK
FIFO_WR
FIFO_RD_N
FIFO_OE_N
FIFO_RXF_N
FIFO_TXE_N

Rules:

Route as grouped parallel bus
Keep traces short
Maintain clean bus ordering
Avoid RF section
Minimize vias

FIFO Trace Width:

0.15 mm minimum
0.20 mm preferred

==================================================

POWER DOMAIN RULES

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Main Rails:

+5V_PROTECTED
+5V_MAIN
+3V3_MAIN

Filtered Domains:

+3V3_RF
+3V3_ADC
+5V_MIXER_RF

Rules:

Wide traces
Short return paths
Ferrite beads close to destination ICs
Bulk capacitors near filtered domains
Decoupling capacitors immediately beside IC power pins

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GROUNDING RULES

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Ground Plane:

Layer 2 continuous solid GND plane
Avoid major splits

Stitching Via Rules:

Add stitching vias around RF section
Add stitching vias near ADC
Add stitching vias near USB connector
Add stitching vias around PLL section

Rules:

Preserve RF return path continuity
Avoid routing that cuts RF return currents

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DECOUPLING RULES

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General Rules:

Every IC power pin requires local decoupling
Capacitors must be very close to power pins
Use shortest possible GND path

Preferred Capacitors:

100nF ceramic for HF decoupling
10uF ceramic for bulk local filtering

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KEEP OUT ZONES

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RF Keepout:

No USB traces through RF region
No FIFO bus through RF region
No switching regulators near RF traces

PLL Keepout:

No digital clocks near PLL filter
No switching power traces near PLL section

ADC Keepout:

Avoid noisy digital routing near ADC analog input

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ROUTING PRIORITY

==================================================

Priority Order:

RF traces
PLL filter
ADC clock
ADC bus
USB differential pair
FIFO bus
Power traces
LEDs/debug/reset
Remaining GPIO

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DRC CONSTRAINTS

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Minimum Trace Width:

0.15 mm

Preferred Trace Width:

0.20 mm

Power Trace Width:

0.50 mm minimum

Minimum Via Size:

0.30 mm

Minimum Clearance:

0.15 mm

RF Clearance:

Larger preferred around RF traces

==================================================

FINAL VALIDATION CHECKLIST

==================================================

Before PCB Freeze:

Placement:

Verify FPGA orientation
Verify RF chain order
Verify FT2232H near USB connector

Routing:

Verify ADC bus ordering
Verify FIFO bus ordering
Verify USB differential matching
Verify RF isolation

Power:

Verify filtered domains
Verify ferrite bead placement
Verify decoupling placement

Ground:

Verify uninterrupted GND plane
Verify stitching vias

Validation:

Run DRC
Remove airwires
Remove overlapping copper
Verify net connectivity
Verify no floating power pins

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FINAL TARGET

==================================================

Final PCB Goals:

Manufacturable
Low-cost fabrication compatible
Easy manual inspection
RF stable
Clean ADC acquisition
Reliable FPGA streaming
USB stable
Debuggable
Future firmware friendly

Target State: PCB ROUTING READY

SAR Receiver PCB Constraints and Layout Specification
Project Overview
PCB STACKUP
FUNCTIONAL ZONES
COMPONENT PLACEMENT COORDINATES
FPGA ORIENTATION RULES
RF ROUTING RULES
ADC ROUTING RULES
USB ROUTING RULES
FIFO BUS ROUTING RULES
POWER DOMAIN RULES
GROUNDING RULES
DECOUPLING RULES
KEEP OUT ZONES
ROUTING PRIORITY
DRC CONSTRAINTS
FINAL VALIDATION CHECKLIST
FINAL TARGET

Reviews

Documents

Placement Intent

Schematic Freeze Checklist

SAR Receiver PCB Constraints and Layout Specification

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