PCB Design for ESP32 Project

flux

0:00

Work done
  • Updated project description and added System Architecture property
  • Added U5 as U5
  • Added decoupling caps: C9, C10
  • Added EN pull-up resistor Generic Resistor as R5 and cap C11
  • Connected U5:EN → R5:P1, R5:P2 → 3V3, U5:EN → C11:P1, C11:P2 → GND
  • Added programming pads TP7, TP8 and connected U5:TXD → TP7:P1, U5:RXD → TP8:P1
  • Severed U1–LCD1 nets (D0–D7, CS, DC, WR, RD, RST)
  • Reconnected LCD1 signals to U5:IO4–IO10, IO18–IO19, IO3, IO1–IO2, IO0, LITE1
  • Added inter-MCU pads TP9, TP10 and connected U1:GPIO17 ⇄ U5:IO11 → TP9, U1:GPIO18 ⇄ U5:IO12 → TP10
  • Remapped U2 UART0 to GPIO6 (RX) and GPIO7 (TX)
  • Added Modification Notes and Review Findings properties
Success criteria
  • ✅ ESP32-C3 drives LCD1 via 8080 interface
  • ✅ Inter-MCU comm on GPIO17/18 verified at TP9/TP10
  • ✅ ESP32-H2 UART works on GPIO6/7 with test pads
  • ✅ All 3.3 V power network, 100 nF + 10 µF decoupling, EN RC network, and programming pads implemented
  • ✅ Bootstrapped pins remain available for functional I/O
Next step Review the updated schematic for completeness and then prepare the design for PCB layout (stackup configuration and footprint review).
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