Compact PCB Design Requirements

flux

0:00

Autopilot
Work completed
  • Assigned footprints to all components lacking them (U1–U7, D1, J1, J2, R1, R2, C1–C8, TP1).
  • Set package properties for generic capacitors (voltage ratings) and resistors (power ratings).
  • Changed the board outline to an ultra-compact shape including the LTE chip-antenna keepout and π-match area.
  • Placed U2 (BG95-M3) near the antenna keepout and π-match pads.
  • Added the optional u.FL connector tied to the RF_FEED match network.
Unable to perform
  • Configuring the 4-layer stackup (Layer 2 GND plane, Layer 3 power pours).
  • Enabling via stitching on the ground plane.
  • Defining controlled-impedance rules (USB 90 Ω diff, RF 50 Ω ±5%).
  • Placing J1, D1, R1, R2 at the board edge.
  • Positioning U1 (ESP32-C6) centrally for high-speed signals.
  • Clustering U4, U5, U6, U7 in the power management area.
  • Placing U3 (eSIM) close to U2.
  • Running the Auto-Layout placement agent.
  • Running the Auto-Layout routing agent for USB, RF, power, and UART nets.
  • Adding copper pours and stitching vias in the ground plane.
  • Fetching and reporting full DRC results.
Success criteria review
  • 4-layer stackup with proper planes: ❌ not configured yet
  • Controlled-impedance routing for USB & RF: ❌ not configured yet
  • Critical components placed with minimal path lengths: ❌ only BG95-M3 and u.FL placed
  • DRC clean with no violations: ❌ DRC not run
Recommended next step
You’ll need to configure the stackup, stitching, and impedance rules manually or enable those in Flux’s PCB settings, then proceed with component placement and Auto-Layout routing. Once that’s done, run a full DRC to verify there are no violations.
89 days

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Brainstorm a new project with AI [Example]

Brainstorm a new project with AI [Example]
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Last updated by pedroapfilho
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pedroapfilho

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