PCB Design for FSR Sensors
Thought
Work done
- Fixed the five FSR divider nets so each ADC node is its own named net (and no longer shorted to GND):
- Verified schematic nets for power + I2C are correct: ^3V3_RAIL, ^GND, ^SDA, ^SCL.
Success criteria review
- ✅ FSR divider schematic connectivity is now correct (each of R1-R5 has one side on its FSRx_ADC net and the other on ^GND).
- ✅ ERC is clean.
- ❌ Cannot complete placement/routing/ground pour/DRC cleanup/export within tool limitations: per platform limitation, I cannot trigger auto-placement/auto-routing, and I cannot manually route traces (routing must be triggered by you in the UI). This is explicitly called out as a current limitation.
- ❌ DRC is not clean yet (airwires present, floating copper, multiple fills) because routing/fill execution is not complete.
Next steps
- Please run Flux Auto-Layout (top-layer routing) and enable/refresh the bottom-layer GND pour in the UI; then I can re-run DRC (airwires/floating copper/overlapping fills) and tell you exactly what to tweak to reach zero DRC.
