PCB Design for FSR Sensors

flux

0:00

Work done
  • Fixed the five FSR divider nets so each ADC node is its own named net (and no longer shorted to GND):
    • ^FSR1_ADC = J3:P2 + R1:P1 + J1:Pin_3
    • ^FSR2_ADC = J4:P2 + R2:P1 + J1:Pin_4
    • ^FSR3_ADC = J5:P2 + R3:P1 + J1:Pin_5
    • ^FSR4_ADC = J6:P2 + R4:P1 + J1:Pin_6
    • ^FSR5_ADC = J7:P2 + R5:P1 + J1:Pin_7
  • Verified schematic nets for power + I2C are correct: ^3V3_RAIL, ^GND, ^SDA, ^SCL.
Success criteria review
  • ✅ FSR divider schematic connectivity is now correct (each of R1-R5 has one side on its FSRx_ADC net and the other on ^GND).
  • ✅ ERC is clean.
  • ❌ Cannot complete placement/routing/ground pour/DRC cleanup/export within tool limitations: per platform limitation, I cannot trigger auto-placement/auto-routing, and I cannot manually route traces (routing must be triggered by you in the UI). This is explicitly called out as a current limitation.
  • ❌ DRC is not clean yet (airwires present, floating copper, multiple fills) because routing/fill execution is not complete.
Next steps
  • Please run Flux Auto-Layout (top-layer routing) and enable/refresh the bottom-layer GND pour in the UI; then I can re-run DRC (airwires/floating copper/overlapping fills) and tell you exactly what to tweak to reach zero DRC.
27 days
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J1 Pin_1 - J3 P1
J5
J7
J1 Pin_1 - J3 P1
J3 P2 - R1 P1
J2 Pin_7 - J8 PIN_2
J6 P2 - R4 P1
J7 P2 - R5 P1
R1 P2 - R2 P2
J7 P2 - R5 P1
J3 P2 - R1 P1
J5 P2 - R3 P1
J5 P2 - R3 P1
J6
J1 Pin_1 - J3 P1
J5 P2 - R3 P1
J1 Pin_1 - J3 P1
J1 Pin_1 - J3 P1
J8
J2 Pin_7 - J8 PIN_2
J1
J4
J6 P2 - R4 P1
J2
J5 P2 - R3 P1
J4 P2 - R2 P1
J4 P2 - R2 P1
J7 P2 - R5 P1
J6 P2 - R4 P1
J3 P2 - R1 P1
J3
J6 P2 - R4 P1
J4 P2 - R2 P1
J2 Pin_3 - J8 PIN_4
J4 P2 - R2 P1
J6 P2 - R4 P1
J2 Pin_6 - J8 PIN_3
J5 P2 - R3 P1
J3 P2 - R1 P1
J1 Pin_1 - J3 P1
J3 P2 - R1 P1
J1 Pin_1 - J3 P1
J2 Pin_6 - J8 PIN_3
J7 P2 - R5 P1
J4 P2 - R2 P1
J4 P2 - R2 P1
J2 Pin_3 - J8 PIN_4
J5 P2 - R3 P1
J3 P2 - R1 P1
J7 P2 - R5 P1
J7 P2 - R5 P1
J3 P2 - R1 P1
J4 P2 - R2 P1
J6 P2 - R4 P1
J7 P2 - R5 P1
J5 P2 - R3 P1
J1 Pin_1 - J3 P1
J6 P2 - R4 P1
R1 P2 - R2 P2
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Gloves

Welcome to your new project. Imagine what you can build here.

Properties

Diagram



  
    
  
  
    
  



""ESP32 DevKitC V4 Daughterboard""


""FSR inputs x5""


""I2C expansion""



























FSR1_ADC

FSR1_ADC to GND

FSR2_ADC

FSR2_ADC to GND

FSR3_ADC

FSR3_ADC to GND

FSR4_ADC

FSR4_ADC to GND

FSR5_ADC

FSR5_ADC to GND

SCL

SDA to node_3V3

SCL to node_3V3

3V3 pin

GND pin

GND pin

to GND


















C1 node_100nF decoupling
J1 node_1x19 female header
J2 node_1x19 female header
3V3_RAIL power bus
GND pour
J3 FSR1 JST PH 2
R1 node_10k pulldown
J4 FSR2 JST PH 2
R2 node_10k pulldown
J5 FSR3 JST PH 2
R3 node_10k pulldown
J6 FSR4 JST PH 2
R4 node_10k pulldown
J7 FSR5 JST PH 2
R5 node_10k pulldown
J8 JST PH 4 I2C EXP
R6 4.7k SDA pullup
R7 4.7k SCL pullup

Pricing & Availability

Distributor

Qty 1

Arrow

$0.54

LCSC

$0.22

Mouser

$0.65

Verical

$0.32–$17.75

Assets

2.svg

2.svg

2Default

Controls