Routing completed successfully. I’m running final DRC/manufacturing/BOM checks now and will call out any remaining items that need manual sourcing or review.
The small post-route placement adjustment invalidated several existing traces, so I’m clearing the stale routing and running one clean re-route from the final placement.
Completed the PCB layout pass: the board is 50 × 80 mm, 4-layer, placed with the ESP32 antenna intentionally overhanging the top edge, and fully routed with no airwires/overlap/dangling/invalid-layer errors remaining.
Open items:
U1 still reports a body-over-edge warning; this is intentional for the ESP32 antenna keepout.
BOM still needs final MPNs for generic resistors/capacitors, L3 inductor, and J4 header; TP1–TP4 were excluded from BOM/PnP.
Routing used 0.1 mm traces to enter fine-pitch parts, so power paths should be widened/poured before manufacturing.