Smart Espresso Scale


Routing completed successfully. I’m running final DRC/manufacturing/BOM checks now and will call out any remaining items that need manual sourcing or review.
The small post-route placement adjustment invalidated several existing traces, so I’m clearing the stale routing and running one clean re-route from the final placement.
Created a project doc

Layout Verification Notes — Smart Espresso Scale

View Document

Board set to compact 50 x 80 mm rounded rectangle. Stackup set to Standard 4 Layer.
Completed the PCB layout pass: the board is 50 × 80 mm, 4-layer, placed with the ESP32 antenna intentionally overhanging the top edge, and fully routed with no airwires/overlap/dangling/invalid-layer errors remaining.
Open items:
  • U1 still reports a body-over-edge warning; this is intentional for the ESP32 antenna keepout.
  • BOM still needs final MPNs for generic resistors/capacitors, L3 inductor, and J4 header; TP1–TP4 were excluded from BOM/PnP.
  • Routing used 0.1 mm traces to enter fine-pitch parts, so power paths should be widened/poured before manufacturing.
I documented the verification details in Layout Verification Notes.
Suggested next steps:
  1. Select final passive/inductor/header MPNs.
  2. Widen/pour VBUS, BAT, SYS, REG_IN, and 3V3 power paths.
  3. Verify antenna keepout visually/mechanically.
  4. Export Gerbers/BOM/PnP once BOM MPNs are finalized.
Finalize BOM and power
Select final MPNs
Widen power paths
Verify RF keepout
Run manufacture export

J1
U4
U3
J5
U1
R5
Resistance
2.94kΩ
C16
Capacitance
100nF
R10
Resistance
10kΩ
R15
Resistance
10kΩ
R16
Resistance
10kΩ
C10
Capacitance
1uF
R21
Resistance
330kΩ
R1
Resistance
5.1kΩ
R8
Resistance
1.5kΩ
R7
Resistance
46.4kΩ
C7
Capacitance
10uF
C1
Capacitance
10uF
C2
Capacitance
10uF
C8
Capacitance
10uF
R20
Resistance
1MΩ
R14
Resistance
4.7kΩ
C4
Capacitance
10uF
C3
Capacitance
22uF
R2
Resistance
5.1kΩ
R9
Resistance
10kΩ
R6
Resistance
10kΩ
R19
Resistance
100Ω
R17
Resistance
10Ω
C9
Capacitance
100nF
C12
Capacitance
10uF
C13
Capacitance
100nF
R4
Resistance
3.57kΩ
C6
Capacitance
10uF
C14
Capacitance
10nF
R13
Resistance
4.7kΩ
C11
Capacitance
10uF
R12
Resistance
10kΩ
C15
Capacitance
100nF
R11
Resistance
10kΩ
C5
Capacitance
100nF
R18
Resistance
100Ω
R3
Resistance
3.09kΩ
TP4
J4
C17
Capacitance
10uF
J3
F1
TP3
SW1
D2
TP1
SW2
TP2
D3
SW5
L3
Inductance
1.5uH
SW4
J2
D1
SW3
U2
Project Specification — Smart Espresso Scale
Project Overview
Status: Draft schematic complete.
Battery-powered smart espresso scale with load-cell measurement, local OLED display, ESP32-C3 wireless MCU, USB-C charging, power-path management, and programming/debug access.
Intended Use
  • Countertop espresso scale for weighing coffee dose and espresso output.
  • Prototype/validation build, not yet production certified.
  • Expected environment: moisture, steam, heat, coffee residue, and user handling.
What the Device Should Do
  • Measure weight from a 4-wire strain-gauge load cell.
  • Display weight/tare/timer data on an I2C OLED module.
  • Support tare and mode/timer buttons.
  • Run from a protected 1S LiPo battery and charge over USB-C.
  • Provide programming/debug access for ESP32-C3 firmware.
  • Monitor battery voltage in firmware.
Main Features
  • ESP32-C3-WROOM-02-N4 WiFi/BLE module.
  • HX711 24-bit load-cell ADC.
  • USB-C 5V sink input with CC pull-downs, VBUS fuse, and VBUS TVS.
  • BQ24074 power-path LiPo charger to support run-while-charging behavior.
  • TPS63031 fixed 3.3V buck-boost regulator for stable rail across LiPo discharge.
  • I2C OLED header, tare/mode buttons, reset/boot controls, UART programming header.
  • Filtered HX711 analog/excitation rail and load-cell input filter.
System Architecture

Diagram


USB-C node_5V 500mA PTC + TVS BQ24074 power-path charger Protected node_1S LiPo SYS rail Power switch TPS63031 3.3V buck-boost 3V3 rail ESP32-C3-WROOM-02 I2C OLED header HX711 analog filter HX711 4-wire load cell Tare/Mode buttons UART/EN/BOOT header VBAT divider
Hardware Subsystems
  • Power input: J1 USB-C sink, R1/R2 5.1k CC pull-downs, F1 500mA PTC, D1 VBUS TVS.
  • Charger/power path: U3 BQ24074, J2 LiPo, 250mA programmed fast charge, ~500mA input current limit, charge LED.
  • 3.3V rail: U4 TPS63031 with 1.5uH inductor and 2x10uF output capacitance.
  • MCU: U1 ESP32-C3-WROOM-02-N4 with EN RC reset, GPIO2/GPIO8/GPIO9 boot strapping, UART programming header.
  • Measurement: U2 HX711 at 10SPS, internal oscillator, 3.3V filtered excitation, 100Ω input series resistors and 10nF differential input cap.
  • UI: J4 I2C OLED header, SW1 tare, SW2 mode/timer.
  • Debug/test: J5 UART/EN/BOOT header, TP1 3V3, TP2 GND, TP3 BAT, TP4 HX711_DOUT.
Interfaces and Connections

Table


InterfaceNets / PinsNotes
USB-C powerVBUS_RAW, VBUS, CC1, CC2Charging only; D+/D-/SBU left NC.
BatteryBAT, GNDUse protected 1S LiPo pack.
Load cellE+, E-, A+, A-J3 pinout: 1=E+, 2=E-/GND, 3=A+, 4=A-.
OLED3V3, GND, I2C_SDA, I2C_SCLJ4 pin labeled 5V is intentionally powered from 3V3.
Programming3V3, GND, UART_TXD, UART_RXD, ESP_EN, ESP_BOOT_GPIO9J5 uses AVR-ISP footprint but reassigned for ESP32-C3.
Power and Runtime Expectations
  • Battery: protected 1S LiPo, assumed 500–1000mAh.
  • Charger: ~250mA fast charge; charger TS uses fixed 10k resistor because no pack NTC is currently connected.
  • System can run while USB is attached through BQ24074 power path.
  • Firmware should disable or quiet WiFi/BLE during HX711 sampling for best noise performance.
Power Tree and Power Budget

Table


RailLoadTypicalPeak / Notes
3V3ESP32-C3 module80–150mA active300–500mA RF bursts; regulator selected around this.
3V3HX711 + load cell excitation~2–5mADepends on load-cell bridge resistance.
3V3OLED module10–30mAPixel-dependent pulses; C11 local bulk added.
3V3Buttons/dividers/pullups<1mAVBAT divider ~3uA continuous.
USB/BAT inputCharger/system<=500mA USB input targetBQ24074 input limit ~500mA, charge current ~250mA.
Manufacturing and Assembly Expectations
  • SMD-first prototype design with through-hole headers/connectors where useful.
  • Needs PCB layout with ESP32 antenna at board edge and no copper under antenna keepout.
  • Add splash/moisture protection at enclosure level before production use.
  • Verify generic inductor package/MPN and current rating before fabrication.
Firmware-Relevant Hardware Requirements
  • HX711: DOUT=GPIO0, SCK=GPIO1.
  • I2C OLED: SDA=GPIO5, SCL=GPIO6.
  • Buttons: TARE=GPIO4, MODE=GPIO7, active-low.
  • Battery sense: GPIO3 via 1M/330k divider and 100nF filter.
  • ESP32-C3 boot: GPIO9 button pulls low, EN reset button pulls low.
Physical Design Expectations
  • Keep HX711 and J3 load-cell connector away from ESP32 antenna and switching regulator.
  • Route A+/A- as a quiet differential pair/adjacent traces; avoid OLED/I2C/regulator switching near them.
  • Place TPS63031 inductor and capacitors very close to U4.
  • Place ESP32 antenna at PCB edge with manufacturer keepout.
Important Design Decisions
  • Used BQ24074 instead of MCP73831 to avoid charger termination/load-sharing problems during run-while-charging.
  • Used TPS63031 buck-boost rather than LDO so 3.3V remains regulated across most of LiPo discharge.
  • USB-C is charging-only to avoid adding USB data ESD/routing complexity; programming is via UART header.
  • HX711 runs at 10SPS for better 50/60Hz rejection and low-noise scale readings.
Assumptions
  • User accepts a protected LiPo pack; no on-board pack protection IC is currently included.
  • OLED module is 3.3V-compatible.
  • Load cell is a 4-wire bridge; no shield pin is included on J3.
  • Target is prototype/validation; regulatory certification is not complete.
Change Notes
  • Initial schematic created with 60 components and 36 nets.
  • ERC selected checks reported no open electrical/passive/component warnings; layout airwires remain expected before PCB routing.
  • Project Overview

  • Intended Use

  • What the Device Should Do

  • Main Features

  • System Architecture

  • Hardware Subsystems

  • Interfaces and Connections

  • Power and Runtime Expectations

  • Power Tree and Power Budget

  • Manufacturing and Assembly Expectations

  • Firmware-Relevant Hardware Requirements

  • Physical Design Expectations

  • Important Design Decisions

  • Assumptions

  • Change Notes