Manufacturing Readiness Checklist

flux

1:39

Project
BOM
PCB Layout
Review (ERC/DRC)
Schematic

Using Schematic Tool.

Using PCB Layout Tool.

Using Review (ERC/DRC) Tool.

Using BOM Tool.

Checking.

Evalu.

Here’s a manufacturing-readiness pass on your design, starting with the BOM and then walking through the rest of the checklist.
1) BOM review BOM summary
  • Good news: most populated parts have valid MPNs and current source coverage.
  • Main blockers are:
    • Obsolete / unavailable regulator: U2
    • Unavailable crystal: Y1
    • Missing real MPNs on connectors: J4, J5, and review also flags J2
    • Generic / placeholder capacitor: C2
BOM issues to fix first

Critical sourcing blockers

ItemIssueWhy it mattersRecommended action
U2Obsolete, stock effectively unavailableManufacturing risk / redesign riskReplace with a currently active LDO
Y10 stock in reviewImmediate procurement blockerReplace or pre-approve alternate
C2Generic part, MPN=OPTNot manufacturable as-isAssign a real manufacturer + MPN
J4No MPNAssembly house cannot source deterministicallyAssign exact header part
J5No MPNSame as aboveAssign exact header part

Lower-priority BOM concerns

ItemIssueNote
J2Review says no MPN, schematic shows part name onlyLikely property mismatch; verify BOM field mapping
MCU_TXD, MCU_RXD, MCU_BOOTNo stock dataUsually acceptable if these are custom/test pads, but confirm fab footprint is standard
IC1Manufacturer shown as TI in BOM context, but project constraint says Espressif ESP32-C3 familyFix metadata so purchasing docs are clean

Cost optimization opportunities

OpportunityObservationLikely impact
Standard passives already consolidatedR1, R3, R5 share one MPN; R2, R4 share one MPN; many capacitors are already groupedGood
Review 0805 capacitor mixC1, C17, C21, C22, C30, C19 are intended as one family, but C19 shows 12 uF while the same MPN elsewhere shows 10 uFClean up property inconsistency before release
Mouser-only dependence on some 1 uF partsmany of the C3/C5/C7-family entries show practical stock mainly at Mouser in reviewConsider second-source if volume matters
RF / specialty partsY2, L4, L1 are more specializedKeep alternates approved if production scale increases
BOM release checklist
  • Replace obsolete U2
  • Replace unavailable Y1
  • Convert C2 from generic to real MPN
  • Add real MPNs to J4 and J5
  • Verify BOM property mapping on J2
  • Resolve inconsistent capacitance metadata on C19
  • Correct manufacturer metadata on IC1
2) Design rule / connectivity review Current DRC/ERC status
  • 53 airwire errors
  • 6 single-pin nets
  • No missing-footprint errors
  • No undriven-net errors in the fetched review set
Connectivity issues found

Single-pin nets

NetFindingLikely meaning
Net 28U1 XOUT onlyUnused oscillator pin or incomplete crystal connection
Net 37U1 XIN onlySame concern
Net 34J1 CMD onlySD interface incomplete / intentionally unused but not marked NC
Net 30J1 DAT2 onlySame
Net 36J1 CD onlyCard-detect left floating or unused
Net 7Y2 pin 2 onlyAntenna second pad likely intentionally floating depending on footprint, but verify against datasheet/land pattern intent
Manufacturing implication
  • The board is not layout-ready yet because of the large airwire count.
  • The single-pin nets need to be explicitly resolved:
    • If intentional, mark or document them properly.
    • If accidental, finish the schematic/net definitions before fab release.
Priority actions
  • Close all airwires before generating fabrication outputs.
  • Verify whether U1 crystal-related pins are intentionally unused.
  • Verify whether unused pins on J1 should be NC or connected.
  • Verify whether Y2 pad 2 is intentionally unconnected per its recommended layout.
3) Passive consolidation opportunities

Already well consolidated

Value familyConsolidation status
10 kΩ 0402Good: R1, R3, R5
100 Ω 0402Good: R2, R4
1 uF 0402Good: C3, C5, C7, C9, C10, C11, C12, C13, C15, C18, C20, C24
100 nF 0402Good: C23, C28, C31
13 pF 0402Good: C4, C8
10 uF 0805 familyMostly consolidated, but property mismatch exists on C19
Consolidation candidates
  • Replace placeholder C2 with a real stocked MPN and see whether it can share a family already used elsewhere.
  • Normalize C19 metadata to match the rest of its MPN group if it is truly the same part.
  • Consider whether C27 and C29 can share the same approved AVL as other bulk input caps in your purchasing flow.
Verdict
  • Passive consolidation is mostly good already.
  • Biggest win is not part-count reduction, but cleanup of placeholder/inconsistent metadata.
4) Footprint / package verification for assembly What looks good
  • Review reports no missing footprints.
  • The following critical parts have assigned footprints/models in layout:

Items needing manual verification before release

ItemConcernCheck
C2Generic placeholder with 0603 package onlyConfirm the intended footprint and source part exactly match
IC1Part naming/metadata inconsistencyConfirm exact ESP32-C3 package and land pattern
U2Footprint exists, but part is obsolete anywayRe-verify footprint after replacement
J4, J5Generic headersConfirm the exact hole size, pitch, and assembly style required
J1Placed on inverted sideConfirm assembly side and stencil expectations
Y2RF antenna footprint is sensitiveVerify keepout/orientation against vendor land pattern
Y1Needs replacement due to availabilityRecheck pad geometry if alternate selected
Footprint release verdict
  • No missing footprints
  • But footprint verification is not complete until placeholder and generic parts are replaced with final production MPNs.
5) Board bring-up test plan Bring-up goals
  • Confirm no shorts
  • Verify power rails
  • Confirm boot/debug access
  • Confirm MCU operation
  • Confirm ADC/load-cell path
  • Confirm storage and GPIO interfaces
Suggested bring-up sequence Stage 1 - Pre-power inspection
  • Visual inspection under microscope
  • Check polarity/orientation for ICs, connectors, and polarized placement assumptions
  • Measure resistance from each power rail to GND with power off
  • Confirm no solder bridging on fine-pitch devices:
Stage 2 - First power-on
  • Power from current-limited bench supply through J2
  • Start with low current limit
  • Check rails in order:
    • PP12V0
    • PP5V0
    • PP3V3
  • Verify regulator outputs and ripple with oscilloscope
Stage 3 - MCU access
  • Use MCU_TXD, MCU_RXD, and MCU_BOOT
  • Confirm boot mode entry
  • Confirm serial download / flashing
  • Run minimal firmware:
    • heartbeat GPIO
    • UART banner
    • ADC interrupt visibility
Stage 4 - Peripheral checks
  • Verify I2C pull-ups and bus activity on:
  • Confirm U1 responds over I2C
  • Check INT_ADC_DRDY interrupt behavior
  • Validate load-cell input path through J3
  • Validate switch/header interface on J4 and J5
  • Validate MicroSD interface on J1 if intended for first spin
Stage 5 - Functional calibration
  • Zero-scale reading
  • Known weight calibration
  • Noise floor measurement
  • Repeatability test
  • Long-duration drift test
  • Brownout / power-cycle test

Bring-up checklist table

TestPass criterion
Visual inspectionNo tombstones, bridges, missing parts
Rail shortsNo low-ohmic short to GND on primary rails
12 V inputStable at connector input
5 V railPresent and within tolerance
3.3 V railPresent and within tolerance
MCU bootDevice enters boot/program mode
UARTBoot logs / firmware banner visible
I2CACK from ADC
ADC DRDYInterrupt toggles as expected
Load-cell inputStable raw readings with no load
CalibrationKnown-mass reading within target error
Reboot behaviorClean restart across repeated cycles
Overall manufacturing readiness verdict Status
  • Not ready for fabrication release yet
Must-fix before release
  • Resolve sourcing blockers: U2, Y1, C2, J4, J5
  • Close 53 airwires
  • Resolve or intentionally document the 6 single-pin nets
  • Clean BOM metadata inconsistencies, especially C19, J2, and IC1
If you want, I can do the next pass as a release blocker list ranked by severity or help you identify replacement candidates for U2 and Y1.
Find U2 replacement
Find crystal replacement
Check remaining DRC
5 days

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USBC2.0_D_N
USBC2.0_D_P
SPI_SCK
IC1
Manufacturer Name
TI
Manufacturer Part Number
ESP32-C3
INT_ADC_DRDY
GPIO_SW1
I2C_SDA
GPIO_SW2
SPI_MISO
SPI_MOSI
I2C_SCL
SPI_CS
PP3V3
SPI_CS
SPI_MOSI
MCU_TXD
J1
Manufacturer Name
Wayne Enterprises
MCU_RXD
MCU_BOOT
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ESPRSSO32 Smart Scale AI Auto Layout [Example]

ESPRSSO32 Smart Scale AI Auto Layout [Example]
Description

Created
Last updated by natarius
1 Contributor(s)
natarius

Controls

Properties

Vendor family constraint
a) Must stay in the ESP32‑C3 family only (Espressif vendor, RISC‑V C3 core)

Availability & Pricing

DistributorQty 1
Arrow$3.41–$6.11
Digi-Key$6.29–$10.05
LCSC$7.44–$8.37
Mouser$10.61
TME$3.40
Verical$3.38–$4.95

Assets