Embedded AI Processor Recommendation
Thought for 2 mins 52 sec
The schematic PDF is readable and shows several important differences from the current Flux design, including added DW01A/FS8205A battery protection and an AT2659 RF stage. The STEP file did not load in the first inspection, so I’m retrying the mechanical review separately while verifying the current Flux layout and stack-up.
Thought for 5 sec
Review started but is blocked because no ACUs are currently available.
Completed:
- Inspected the schematic PDF and extracted its major circuits, components, and nets.
- Flagged preliminary concerns: limited USB protection, charging-only USB implementation, power-tree/current-capacity validation, RF-layout dependence, and incorrect
U10inductor designator. - Confirmed the PDF includes DW01A/FS8205A battery protection and AT2659 RF circuitry not reflected in the current Flux BOM.
Remaining:
- Inspect the STEP model and physical placement.
- Verify the current Flux schematic, footprints, stack-up, keepouts, and DRC state.
- Complete power, signal, RF, thermal, and manufacturability analysis.
- Generate the production-readiness review report and rating.
No project changes were made.
Retry full review
List mismatches
Inspect STEP placement
Check missing circuits
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Schematic Completion Plan
Status: approved ready-to-execute plan for when ACUs are available. PCB layout must not start until this plan is completed, ERC is reviewed, an updated schematic review report is generated, and the user explicitly approves the schematic.
Design Decisions Locked for Schematic Completion
- Compute: Radxa Zero 3W, 4 GB preferred, eMMC variant preferred.
- OS/storage: Radxa eMMC if available; carrier microSD mainly for removable data export.
- microSD chip-select: Radxa pin 29 preferred.
- Radxa pin 26: reserve/no-connect until exact board revision is verified.
- AS7341: Rev A uses a connectorized AS7341 + LED-ring optical-head assembly, not bare IC integration on the main carrier.
- Optical-head policy: keep the optical head modular for Rev A so optical geometry can be tested and revised without redesigning the main carrier PCB.
- Runtime policy: treat 6–8 hour runtime as aspirational unless measured power supports it; prioritize reliable operation and accurate power-budget reporting over forcing runtime assumptions.
- I2C: I2C3 for AS7341 optical head and MAX17048.
- GPS: UART2 for ATGM336H GPS.
- SPI: SPI3 shared by TFT and carrier microSD, with separate chip-selects.
- Required load switches: GPS, LCD backlight, optical head, LED ring.
- Required test points: USB_5V, BAT, SYSBAT, 5V, 3V3, I2C, UART, SPI, LED rail, and shutdown signals.
- Required optional current-sense/test shunts: 5 V rail and LED rail.
- Stop after schematic wiring, ERC, and schematic review report. Do not start PCB layout until the user approves the schematic.
Execution Sequence
1. Net Naming and Power Domains
Create or confirm these rails/nets:
- USB_5V
- BAT
- SYSBAT or PMID/SYS power-path node
- 5V_SYS
- 3V3_SYS
- 3V3_GPS_SW
- 3V3_OPTICAL_SW
- LCD_BL_SW or LCD_BL_PWR
- LED_RAIL_SW
- GND
- I2C3_SDA / I2C3_SCL
- UART2_GPS_TX / UART2_GPS_RX / GPS_PPS
- SPI3_MOSI / SPI3_MISO / SPI3_SCLK / LCD_CS / SD_CS_PIN29
- LED_DIM_PWM / LED_RING_EN / LED_FAULT
- GPS_EN / LCD_BACKLIGHT_EN / OPTICAL_HEAD_EN
- PWR_BTN / SYS_EN / RADXA_SHDN_REQ / RADXA_WAKE_OR_HOLD
2. Radxa 40-Pin Header Wiring
Wire:
- Pins 2 and 4 to 5V_SYS with adequate power labeling.
- GND pins 6, 9, 14, 20, 25, 30, 34, 39 to GND.
- Pin 3 to I2C3_SDA.
- Pin 5 to I2C3_SCL.
- Pin 7 to LED_DIM_PWM.
- Pin 8 to UART2_GPS_TX / GPS_RX direction label.
- Pin 10 to UART2_GPS_RX / GPS_TX direction label.
- Pin 11 to GPS_PPS optional.
- Pins 12/13 to LCD_DC and LCD_RESET.
- Pin 15 to BUTTON_MEASURE.
- Pins 19/21/23 to SPI3_MOSI/MISO/SCLK.
- Pin 24 to LCD_CS.
- Pin 29 to SD_CS_PIN29.
- Pin 31 to LCD_BACKLIGHT_EN.
- Pins 32/33 to safe-shutdown/power-hold nets.
- Pins 35/36 to user buttons.
- Pin 37 to LED_FAULT or status GPIO.
- Pin 38 to LED_RING_EN.
- Pin 40 to AS7341_INT optional.
Do not wire pin 26 to microSD CS; mark it reserved/no-connect pending Radxa revision verification.
3. USB-C Input and MP2667 Charger / Power Path
Complete:
- USB-C VBUS to USB_5V through protection/fuse path as selected.
- CC1/CC2 pull-downs for 5 V sink operation.
- USB ESD protection as available.
- MP2667 input, battery, system/power-path node, charge-current programming, status pins, and required capacitors/resistors.
- Battery connector to BAT with polarity labeling and protection assumptions.
- MAX17048 battery sensing on I2C3 and alert optional.
Validation notes to add in schematic properties or review report:
- Charge current setting.
- Input current limit.
- Expected simultaneous charge/load behavior.
- Thermal concerns if Radxa runs at high load while charging.
4. TPS61088 5 V Boost Support
Complete:
- SYSBAT input to TPS61088 boost input.
- Inductor, feedback divider, compensation/soft-start if required, enable control, input/output capacitors, and PG/status if available.
- 5V_SYS output to Radxa pins 2/4 and downstream rails.
- Optional current-sense/test shunt footprint in 5V_SYS path.
- Test point on 5V_SYS.
Validation notes:
- Design for at least 2.5 A 5 V peak target if possible.
- Confirm inductor saturation current and thermal margin.
- Confirm battery path can support low-battery input current.
- Do not manipulate assumptions to claim 6–8 hour runtime; report expected runtime from measured/estimated load honestly.
5. 3.3 V Regulator Support
Complete:
- LMR33630 input from 5V_SYS or selected upstream node.
- Inductor, feedback divider, EN, bootstrap/compensation as required by the part, input/output capacitors.
- 3V3_SYS test point.
- Distribution to low-current peripherals and load switches.
Validation notes:
- Confirm chosen input source and efficiency tradeoff.
- Keep 3.3 V noise away from GPS and optical head in layout.
6. Load Switches
Add or complete load-switch circuits for:
- GPS: 3V3_SYS -> 3V3_GPS_SW, controlled by GPS_EN.
- Optical head: 3V3_SYS -> 3V3_OPTICAL_SW, controlled by OPTICAL_HEAD_EN.
- LCD backlight: source rail per final display -> LCD_BL_SW, controlled by LCD_BACKLIGHT_EN.
- LED ring: LED input rail -> LED_RAIL_SW, controlled by LED_RING_EN or a separate LED_PWR_EN.
Requirements:
- Defined boot-safe pull states.
- Test point or accessible output pad for each switched rail where practical.
- Clear enable polarity in component properties or net naming.
7. Peripheral Wiring
Modular AS7341 + LED-Ring Optical-Head Connector
- Wire 3V3_OPTICAL_SW, GND, I2C3_SDA, I2C3_SCL, optional AS7341_INT.
- Include the LED-ring drive/control interface needed by the selected LED driver topology.
- Add optional series resistors/0-ohm links for I2C if cable length is uncertain.
- Add connector pin labels for optical-head harness.
- Keep the optical-head connector definition flexible enough for Rev A geometry experiments without main-carrier redesign.
GPS
- Wire 3V3_GPS_SW, GND, UART2 TX/RX, optional PPS.
- Add GPS antenna/RF notes and keepout warning in properties or review report.
TFT LCD / Touch
- Wire SPI3, LCD_CS, LCD_DC, LCD_RESET, backlight power/enable, GND, 3.3 V logic.
- Touch interface depends on final module: I2C3 or SPI3.
microSD
- Wire SPI3_MOSI/MISO/SCLK and SD_CS_PIN29.
- Wire 3.3 V, GND, card detect optional.
- Add ESD/protection if externally accessible.
LED Driver / LED Ring
- Wire LED_RAIL_SW, LED_DIM_PWM, LED_RING_EN, LED_FAULT, current-setting components, LED connector/output.
- Add optional LED rail current-sense/test shunt footprint.
- Add test point on LED rail and LED driver control nets.
Buttons and Status LEDs
- Wire measurement/menu/back buttons with pull-ups/pull-downs.
- Wire charge/status/fault LEDs with current-limiting resistors.
- Ensure safe-shutdown button behavior is distinct from regular GPIO buttons.
8. Test Points
Add test points for:
- USB_5V
- BAT
- SYSBAT
- 5V_SYS
- 3V3_SYS
- I2C3_SDA / I2C3_SCL
- UART2_GPS_TX / UART2_GPS_RX
- SPI3_MOSI / SPI3_MISO / SPI3_SCLK / LCD_CS / SD_CS_PIN29
- LED_RAIL_SW
- LED_DIM_PWM / LED_RING_EN
- PWR_BTN / SYS_EN / RADXA_SHDN_REQ / RADXA_WAKE_OR_HOLD
- Charger STAT/PG if available
9. ERC Readiness Pass
Before running ERC, check:
- Every IC power pin is connected to a named rail and has decoupling.
- Every passive has value/rating/package properties.
- Every connector pin is labeled with clear direction/purpose.
- Every enable pin has a defined logic state.
- No I2C/SPI/UART net is accidentally shorted by copied labels.
- Radxa pin 26 is not used for a required function.
- All power rails have source/load direction clear enough for ERC.
- Intentional no-connect pins are explicitly marked.
10. Review Report After ERC
Create an updated schematic review report covering:
- Completed net wiring summary.
- Power-path assumptions and validation gaps.
- TPS61088 sizing notes.
- MP2667 charge/load compatibility notes.
- Runtime estimate policy: 6–8 hour target is aspirational unless measured power supports it.
- Modular optical-head implementation and remaining geometry risks.
- Load-switch default states.
- Test point coverage.
- Remaining unresolved datasheet/footprint/pinout risks.
- ERC result summary and fixes applied.
Stop Condition Before PCB Layout
Stop after schematic wiring, ERC, and schematic review report. Do not begin PCB layout until:
- The user explicitly approves the schematic.
- ERC is reviewed and critical issues are fixed or explicitly waived.
- The schematic review report is created.
- Radxa pinout/revision verification status is recorded.
- Final TFT and GPS antenna implementation are selected or clearly marked as provisional.
Design Decisions Locked for Schematic Completion
Execution Sequence
1. Net Naming and Power Domains
2. Radxa 40-Pin Header Wiring
3. USB-C Input and MP2667 Charger / Power Path
4. TPS61088 5 V Boost Support
5. 3.3 V Regulator Support
6. Load Switches
7. Peripheral Wiring
8. Test Points
9. ERC Readiness Pass
10. Review Report After ERC
Stop Condition Before PCB Layout
