Industrial Controller Board Design

flux

Work done
  • The project direction and implementation plan are already defined for the industrial controller board based on U1-class architecture: ESP32-C3, RS-485, protected 12 V to 24 V input, isolated digital inputs, sensor interfaces, and edge-accessible debug.
  • The current plan also records the required debug network around R1, R2, and C1, the protected input stage around D1 and D2, the buck stage around U2, and isolated I/O / RS-485 sections using U3, U4, and IC1.
  • The required permanent requirements record is already referenced in Project Specification.
Success criteria review
  • ✅ Functional requirements are captured in the project plan and specification, including power, debug access, isolated inputs, and interface goals
  • ✅ The project already has a defined completion plan for schematic and PCB-constraint work
  • ❌ I could not execute any new schematic, component, net, or PCB-constraint changes in this session
  • ❌ I could not verify or complete the remaining implementation items against the live project state
Next steps
I am blocked from continuing execution in this session, so the remaining work is still to be done in the project: finalize connector choices, wire the protected input and 3.3 V rail, complete U1 core/debug nets, finish RS-485 and DI circuitry, connect the I2C/SPI/ADC headers, run reviews, and then add PCB layout constraints for the antenna keepout and isolation spacing. If you re-run this in a session with execution available, I can continue from the current plan and finish the implementation.

flux

Work done
  • The project direction and implementation plan for the industrial controller board were already established, including the ESP32-C3 module, protected 12 V to 24 V input, 3.3 V buck stage, isolated RS-485, opto-isolated DI channels, dedicated I2C/SPI/GPIO connectors, and edge-accessible debug connector.
  • The current project state already reflects partial schematic preparation from that plan: key components such as U1, IC1, U2, U3, U4, U5, U6, U7, J1, J2, J3, J4, J5, D1, D2, L1, R1 through R9, and C1 through C8.
  • The project documentation was also already prepared, including the Project Specification with the block diagram, initial pin allocation, and layout constraints.
Success criteria review
  • ❌ I could not execute the remaining schematic wiring, connector replacement/finalization, review, or layout-constraint edits in this session.
  • ❌ I could not verify final electrical completeness or PCB placement-rule implementation directly.
  • ✅ The requested requirements and remaining implementation steps are clearly captured, so work can resume from a well-defined state.
Next steps
The remaining work is to finish the schematic implementation and verification: finalize the connector strategy, wire the protected input and 3.3 V rail, complete the ESP32 reset/boot/debug network, implement the isolated RS-485 field side and its protection/supply details, finish both opto-isolated DI channels, connect I2C/SPI/ADC interfaces, then run schematic review and add layout constraints for antenna keepout and isolation spacing. When execution access is available again, I can continue from that point.
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Schematic

Layout

3D View

Project Specification
Overview
Industrial controller board based on an ESP32-C3-WROOM-02 module with isolated RS-485 communications, protected 12V-24V DC input, opto-isolated digital inputs, expansion interfaces, and a production-friendly debug header.
Architecture
Diagram



  
    
  
  
    
  
































12V to node_24V DC Input
Reverse Polarity and Surge Protection
3.3V Buck Regulator
ESP32-C3-WROOM-02
Isolated RS485 Power Domain
Isolated RS485 Transceiver
RS485 Field Connector
Opto Isolated DI1
Opto Isolated DI2
KF127 node_2P Input 1
KF127 node_2P Input 2
I2C JST PH 2.0
SPI JST PH 2.0
4x GPIO JST PH 2.0
5 Pin Debug Header
3.3V Sensor Power Output
Functional Requirements
  • MCU: ESP32-C3-WROOM-02 module
  • Input power: 12V-24V DC with reverse polarity and surge protection
  • Main rail: 3.3V buck regulator sized for ESP32, isolated transceiver logic, and external sensor power
  • RS-485: isolated half-duplex interface with 120 ohm termination and TVS protection on bus lines
  • Digital inputs: 2 channels, opto-isolated, compatible with NPN sensors, using PC817 and KF127-2P connectors
  • External interfaces: 1x I2C, 1x SPI, 4x GPIO with analog and digital capability
  • Debug/programming: 5-pin edge-accessible connector exposing GPIO21 TXD, GPIO20 RXD, GND, EN, GPIO9
  • Sensor power: exposed 3.3V and GND output
  • Manufacturing: optimize for JLCPCB assembly with LCSC-friendly parts where possible
Pin Assignment Plan

Table

FunctionESP32-C3 Signal
Debug TXDGPIO21
Debug RXDGPIO20
Boot strapGPIO9
I2C SDAGPIO4
I2C SCLGPIO5
SPI MOSIGPIO6
SPI MISOGPIO7
SPI SCKGPIO8
SPI CSGPIO10
RS485 TXGPIO0
RS485 RXGPIO1
RS485 DE/REGPIO2
DI1GPIO3
DI2GPIO18
GPIO/ADC 1GPIO19
GPIO/ADC 2GPIO11
GPIO/ADC 3GPIO12
GPIO/ADC 4GPIO13
Design Constraints
  • ESP32 antenna edge must sit at board edge with all-layer copper and component keepout under and in front of the antenna area.
  • Keep isolated RS-485 bus-side ground separate from logic ground; connect only through the isolation barrier.
  • Place termination resistor and TVS close to the RS-485 field connector.
  • Use one pair of I2C pull-ups only on the board.
  • Add 10k pull-up plus 100nF capacitor on EN and 10k pull-up on GPIO9.
  • External connectors should be placed at board edges for field wiring and production access.
  • Prefer JLCPCB/LCSC available parts; where unavailable in library, document the intended part choice.

  • Overview

  • Architecture

  • Functional Requirements

  • Pin Assignment Plan

  • Design Constraints