MAX86177 PPG Breakout
do it
Thought for 26 sec
I’ll move R3 to the bottom side near U1, clear only the copper obstructing that placement, route the
~INT escape first, then restore the pull-up supply and FFC connection. I’ll finish with a full DRC and update the manufacturing review.Worked for 2 mins 28 sec
Bottom-side R3 is electrically valid, but this exact 10 mm-wide layout has no legal via/trace access at that location—even after removing the three conflicting vias. I’m restoring the last safe R3 placement and repairing the displaced MISO/MOSI/VREF routes so the board is not left with new defects.
Worked for 14 mins 19 sec
I tested R3 on the bottom side, removed the three obstructing vias, and attempted all required connections. It still could not route within the 10 mm width, so I restored R3 and repaired the displaced MISO, MOSI, and VREF routing.
Only one airwire remains:
U1:~INT to the otherwise routed INT_N network. The practical fix is relocating/removing R3, widening the board, or using an HDI microvia stackup. Details are updated in Routing and Manufacturing Review.Remove R3 and route
Widen board slightly
Try HDI stackup
Move pullup to adapter
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Project Specification
Project Overview
- Device: Compact MAX86141 reflective PPG breakout.
- Status: Stage 1 schematic implementation.
- Host: Arduino Nano ESP32-class 3.3 V system.
Intended Use
Bench-testable reflective skin-contact PPG prototype for green, red, and infrared measurements. PCB-bottom optical placement is deferred to Stage 3.
What the Device Should Do
- Sequentially drive onboard green, red, and IR emitters.
- Acquire reflected light through an external photodiode and MAX86141 dual-channel optical AFE.
- Communicate over SPI and expose active-low interrupt and hardware-reset controls.
Main Features
- ADI/Maxim MAX86141ENP+ dual-channel PPG AFE, 20-ball WLP.
- OSRAM SFH 7018A integrated 536 nm / 660 nm / 940 nm emitter.
- Vishay VEMD5080X01 visible/NIR PIN photodiode.
- Molex 0512810898 8-circuit, 0.50 mm pitch, dual-contact, non-ZIF right-angle SMT FFC connector.
System Architecture
See Block Diagram project file.
Hardware Subsystems
- Input/LED rail: host 3.3 V directly supplies MAX86141 VLED and LED anodes; local ceramic bulk capacitance handles pulses.
- AFE rail: TPS79318-EP low-noise fixed 1.8 V LDO supplies tied VDD_ANA/VDD_DIG.
- Reset: MAX86141 has no hardware reset pin; header RESET_N drives the active-high LDO EN, so asserting low power-cycles the AFE. Firmware soft reset remains available through register 0x0D[0].
- SPI: SCLK/SDI/CSB accept 3.3 V directly (absolute rating to 6 V, VIH 1.4 V). SDO is translated from 1.8 V to 3.3 V with SN74LVC1T45.
- Interrupt: MAX86141 INT is active-low open drain and is pulled up to 3.3 V.
Interfaces and Connections
Table
| Sensor FFC pin | Net | Function |
|---|---|---|
| 1 | 3V3_PWR | Host power and LED supply |
| 2 | GND | Common return |
| 3 | SCLK | SPI clock, mode 0-compatible timing |
| 4 | MOSI | Host to MAX86141 SDI |
| 5 | MISO | Level-shifted MAX86141 SDO |
| 6 | CS_N | Active-low chip select; default-high pull-up |
| 7 | RESET_N | Active-low AFE rail reset through LDO EN |
| 8 | INT_N | Active-low open-drain interrupt |
SPI data is captured by MAX86141 on rising SCLK and changes on falling SCLK; use CPOL=0, CPHA=0 and no more than 4 MHz. Transactions use 24 clocks for ordinary register access.
Power and Runtime Expectations
Powered only from the host 3.3 V header. No battery or charger.
Power Tree and Power Budget
Baseline firmware assumption: one LED active at a time, 20 mA programmed current, 117.3 us integration plus approximately 6.5 us settling/overhead, 100 samples/s per color, three color exposures per frame. LEDs are not driven simultaneously.
Table
| Rail/load | Continuous/average | Peak |
|---|---|---|
| 1.8 V MAX86141 AFE | use 1.17 mA worst-case active bound | 1.17 mA |
| 1.8 V translator side | =2.2 uF output, 0.01 uF low-leakage BP capacitor. |
- SN74LVC1T45: local 100 nF on each supply; DIR fixed for 1.8 V A-side to 3.3 V B-side.
- CS_N and RESET_N default-high pulls; reset RC filtering; INT_N 3.3 V pull-up.
- PD cathode to PD1_IN, anode to PD_GND; unused PD2_IN tied to PD_GND.
- Keep PD_GND distinct from PCB GND for guarded/shielded routing and join it to GND at exactly one point through R4, a footprint-bearing 0-ohm net-tie link placed near U1.
Manufacturing and Assembly Expectations
- Compact SMD circuitry with exact footprints.
- Sensor-board cable interface is Molex 0512810898. Use an 8-position, 0.50 mm pitch, 50 mm FFC with same-side contacts. The companion host adapter is a separate project; its connector orientation will be selected to produce final straight-through pin order 1-to-1.
- Optional test points on 1V8_AFE and VLED/3V3.
- Generic passives use canonical 0402/0603/0805 footprints, explicit tolerance/voltage rating, Role, and Role Details.
Firmware-Relevant Hardware Requirements
- SPI mode 0, maximum 4 MHz.
- CS_N must idle high.
- RESET_N low removes AFE power; release high and wait for power-ready before configuration.
- INT_N is active-low open drain.
- Internal 32.768 kHz oscillator is used; GPIO1/GPIO2 remain unused in this design.
PCB Footprint Verification — U1 MAX86141ENP+
Verified against the official Analog Devices/Maxim MAX86140/MAX86141 Rev. 5 datasheet (19-100051, Rev. 5, July 2023), package outline 21-100134 (N201A2+1), and ADI Application Note 1891.
- Package body: E = 2.048 ± 0.025 mm, D = 1.848 ± 0.025 mm, height A = 0.50 mm max.
- Array: 20 bumps, 5 columns × 4 rows, no depopulated bumps, 0.40 mm basic pitch; array spans E1 = 1.60 mm and D1 = 1.20 mm.
- Package bump diameter: 0.27 ± 0.03 mm. Original Flux copper lands measured 0.216 mm, within ADI's acceptable 0.20–0.26 mm range but smaller than the recommended value and without an explicit NSMD opening.
- In-project footprint override: all 20 U1 lands are 0.250 mm circular NSMD copper, with +0.025 mm mask expansion (0.300 mm mask opening) and a 0.250 mm paste aperture. This follows AN1891's recommended 250 µm NSMD land and 250 µm stencil aperture for 0.4 mm pitch. Routing should neck into each land at no more than 100 µm, with teardrops where fabrication rules permit.
- Actual footprint geometry readback confirms x = −0.8, −0.4, 0, +0.4, +0.8 mm and y = +0.6, +0.2, −0.2, −0.6 mm, matching the 5×4/0.4 mm array. A1 is at the top-left in the datasheet top view (bump side down); the footprint uses A1/VLED at x = −0.8, y = +0.6 and includes the corresponding corner orientation mark.
- Exact terminal-to-ball mapping confirmed: A1 VLED, A2 SCLK, A3 SDO, A4 SDI, A5 CSB; B1 LED3_DRV, B2 INT, B3 GPIO1, B4 GPIO2, B5 VREF; C1 LED2_DRV, C2 VDD_DIG, C3 GND_DIG, C4 GND_ANA, C5 PD_GND; D1 LED1_DRV, D2 VDD_ANA, D3 PGND, D4 PD2_IN, D5 PD1_IN.
Result: footprint mapping and array geometry are correct; the project-level land/mask override brings the footprint to ADI's preferred NSMD geometry. No severe library-part defect was found, so no part-quality report was required.
PCB Dimensions, Stackup, and Placement
- Board: 20 mm × 30 mm compact rectangle, 1 mm corner radius, 0.25 mm outline keep-in, resized after replacing the large header with the compact FFC connector. Placement is the pre-routing checkpoint; final route feasibility remains to be proven.
- Stackup: Standard 4 Layer, approximately 1.3 mm nominal in the Flux template: Top signal / Mid-Layer 1 reserved as continuous GND plane / Mid-Layer 2 reserved for power distribution and shielding support / Bottom signal. No copper pours or plane polygons have been created in this phase; the inner-layer usage is a routing-phase requirement.
- Component-area fill is 26.6%; routing-aware fill is approximately 48.3%. Post-placement congestion analysis reports adequate routing space.
- D1 and LED1 remain bottom-side on the skin-contact face with an approximately 1–2 mm body gap for an opaque optical barrier; U1 is top-side directly opposite D1. J1 is top-side at the edge opposite the optical head with its FFC insertion mouth accessible.
- LED1 and D1 body edges leave approximately 1.8 mm between them for a future opaque optical barrier. Optical apertures face the bottom/skin side. The barrier is assumed to be an opaque molded wall, gasket, or black epoxy feature added in the mechanical/assembly process; no copper or silkscreen should enter the aperture or barrier corridor.
- U1 is opposite D1 to minimize the cross-board PD1_IN connection. R4 is next to U1 as the only intended PD_GND-to-GND star point. U1 decoupling/VREF/VLED parts are clustered at their corresponding ball sides while preserving WLCSP escape corridors. The U2 LDO and U3 MISO translator form separate compact top-side blocks. Test points remain top-accessible and J1 is edge-accessible.
Placement/DFM Risks and Routing Requirements
- 0.4 mm-pitch WLCSP assembly requires a capable assembler, controlled registration, 4 mil stencil process, and inspection appropriate for hidden joints; hand assembly is not recommended.
- Keep the U1 D4/D5/C5 photodiode-side escape free of unrelated routing. Route PD1_IN first, as short as possible, and guard/shield it with PD_GND; join PD_GND to GND only through R4.
- Preserve an unbroken Mid-Layer 1 GND return plane except for the intentionally managed PD_GND strategy. Do not split the return beneath SPI or LED-current paths.
- Keep copper, solder mask graphics, and silkscreen clear of the optical apertures and the 1.8 mm emitter-detector barrier corridor. Final barrier height/material and skin-contact mechanics remain to be validated in the enclosure/assembly design.
- Bottom-side optics create a double-sided assembly and cleaning requirement. Confirm flux residue and conformal-coating processes do not contaminate the emitter/detector windows.
- Routing is intentionally not started; airwires are expected at this placement checkpoint.
Physical Design Status
- Footprints verified and all 23 components placed.
- Post-placement review found no component-body overlaps, outside-board parts, missing footprints, pad-access problems, or unresolved decoupling-placement warnings.
- Routing, vias, copper pours, and shielding polygons remain out of scope for this phase.
Important Design Decisions
- Replace blocked MAX86177 direction with publicly documented MAX86141.
- Use direct 3.3 V VLED instead of a boost rail for the verified 20 mA baseline.
- Add only one level translator: MAX86141 inputs are 3.3 V-compatible, but its 1.8 V SDO high level is not guaranteed to meet ESP32 3.3 V VIH.
- Implement exposed RESET_N by switching LDO EN because MAX86141 provides only a software reset internally.
Assumptions
- Host provides at least 100 mA on 3.3 V.
- Firmware starts at 20 mA, sequential emitters, 100 frames/s; higher current/duty requires thermal and host-current review.
- Common ground plane will be used, with a guarded/shielded PD_GND region connected to PCB GND only through R4.
Change Notes
- Removed all MAX86177 NDA/library blockers.
- Rebased architecture, interface, optics, and power budget on authoritative public MAX86141 and selected component datasheets.
Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Required Support Circuitry
Manufacturing and Assembly Expectations
Firmware-Relevant Hardware Requirements
PCB Footprint Verification — U1 MAX86141ENP+
PCB Dimensions, Stackup, and Placement
Placement/DFM Risks and Routing Requirements
Physical Design Status
Important Design Decisions
Assumptions
Change Notes
