MAX86177 PPG Breakout
do it
Thought for 26 sec
I’ll move R3 to the bottom side near U1, clear only the copper obstructing that placement, route the
~INT escape first, then restore the pull-up supply and FFC connection. I’ll finish with a full DRC and update the manufacturing review.Worked for 2 mins 28 sec
Bottom-side R3 is electrically valid, but this exact 10 mm-wide layout has no legal via/trace access at that location—even after removing the three conflicting vias. I’m restoring the last safe R3 placement and repairing the displaced MISO/MOSI/VREF routes so the board is not left with new defects.
Worked for 14 mins 19 sec
I tested R3 on the bottom side, removed the three obstructing vias, and attempted all required connections. It still could not route within the 10 mm width, so I restored R3 and repaired the displaced MISO, MOSI, and VREF routing.
Only one airwire remains:
U1:~INT to the otherwise routed INT_N network. The practical fix is relocating/removing R3, widening the board, or using an HDI microvia stackup. Details are updated in Routing and Manufacturing Review.Remove R3 and route
Widen board slightly
Try HDI stackup
Move pullup to adapter
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Block Diagram
Stage 1 Architecture
Text
Separate host-adapter PCB (Arduino Nano ESP32-class host, 3.3 V) ├─ 3V3/PWR ───────────────┬────────────> VLED = 3.3 V (bulk pulse reservoir) │ ├─ TPS79318 LDO ──> 1V8_AFE │ └─ SPI/control pull-ups and MISO translator 3.3 V side ├─ GND ─────────────────────────────────────> common ground plane └─ Adapter FFC connector SCLK, MOSI, CS_N ───────────────────────> MAX86141 3.3 V-tolerant inputs MAX86141 SDO (1.8 V) ─> SN74LVC1T45 ───> MISO (3.3 V) INT_N <──────── open-drain + 3.3 V pull-up RESET_N ───────> active-low hardware reset by controlling LDO EN MAX86141 optical AFE ├─ LED1/2/3 current sinks ─> SFH 7018A green/red/IR cathodes ├─ PD1_IN <─────────────── VEMD5080X01 cathode ├─ PD2_IN tied to PD_GND (unused second channel) └─ PD_GND ── R4 0Ω net tie ──> PCB GND (single point; nets remain distinct for guarded routing) Sensor-board J1: Molex 0512810898, 8p 0.5 mm dual-contact non-ZIF right-angle SMT pin 1..8: 3V3_PWR, GND, SCLK, MOSI, MISO, CS_N, RESET_N, INT_N │ └── 50 mm, 8-position, 0.5 mm FFC, same-side contacts ──> separate adapter-board connector Adapter connector orientation will be matched for final straight-through 1:1 pin order. Optical components are reserved for PCB-bottom skin-contact placement in Stage 3; no PCB sizing or layout is part of Stage 1.
Functional Blocks and Sourcing Gate
Table
| Block | Reference classification | Decision |
|---|---|---|
| MAX86141 AFE | None | Build from official ADI MAX86140/MAX86141 Rev. 5 datasheet and EV-system reference circuit |
| 1.8 V low-noise power | None | TPS79318-EP LDO, enabled by exposed RESET_N |
| LED supply | None | Direct filtered 3.3 V; valid because VLED allows 3.1–5.5 V and selected LEDs meet compliance at the 20 mA baseline |
| Reflective optics | None | SFH 7018A integrated green/red/IR emitter + VEMD5080X01 photodiode |
| Sensor cable interface | None | Molex 0512810898 on sensor board; separate adapter-board project; 8p/0.5 mm/50 mm same-side-contact FFC; final adapter orientation straight-through 1:1 |
No obsolete MAX86177/NDA blocker remains.
Stage 1 Architecture
Functional Blocks and Sourcing Gate
