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Layout Setup Confirmation
Status
PCB layout setup has begun, but schematic signoff is not official yet because ERC still reports 10 relay
NC contact errors. These appear to be the same relay-symbol metadata issue where NC means normally closed contact, but ERC treats it as a no-connect-style pin.Layout Setup Applied
- Board resized from 160 mm x 100 mm to 160 mm x 200 mm.
- 4-layer stackup applied.
- Layer intent follows the Rev D requirement:
- Layer 1: Signal
- Layer 2: GND reference plane
- Layer 3: Power plane
- Layer 4: Signal
- Universal board keepout / clearance set to 2.3 mm to support the required 24V safety creepage rule.
Placement Applied
- All components placed on the top layer.
- CORE-P3 placed at the left board edge.
- CORE-P4A / CORE-P4B placed at the right board edge.
- CM4 and I2C devices grouped near the center-left / upper-center.
- K1-K12 relays arranged in two relay banks with driver components nearby.
- J_SAFETY, PC817, and safety driver parts placed in an isolated top-right safety region.
- J_BUZZ1, J_PROX1, and J_BTN1 placed along an accessible bottom edge.
- Red and amber status LEDs placed near the top edge for visibility.
Density / Routability Result
- Board area: 32,000 mm².
- Component area: about 9,883 mm².
- Fill ratio: about 30.9%.
- Routing congestion check now reports enough routing space after placement.
Routing Status
Routing has not been started yet. The next required workflow checkpoint is placement review before routing. Once placement is accepted, routing should proceed in this order:
- I2C traces first.
- Relay driver nets.
- 24V safety-chain nets with 2.3 mm creepage from logic nets.
Blocking / Open Item
- ERC still reports the relay
NCcontact issue on K1-K8, K11, and K12. The schematic cannot be truthfully marked as fully signed off until the relay symbol metadata is corrected or those 10 ERC errors are formally accepted as justified false positives.
Status
Layout Setup Applied
Placement Applied
Density / Routability Result
Routing Status
Blocking / Open Item
