Designing PeakNode 1 Specifications
Started implementing a plan
Create an updated brief to execute the PeakNode 1 PCB routing pass on a 90×60mm 4-layer board (Top Signal / L2 GND solid / L3 3V3 Power plane / Bottom Signal), preserving RF/GNSS keepouts and SMA placements, and then run DRC to flag airwires, copper overlaps, RF keepout violations, power width violations, and missing decoupling.
What has been done so far
- Confirmed board setup: 90mm × 60mm rectangle and 4-layer stackup with L2 as Ground Plane and L3 as Power Plane.
- Applied baseline global layout rules: min trace width 0.127mm (5 mil), preferred widths 0.127mm/0.508mm/1.016mm (5/20/40 mil), hole size 0.3mm, via options noted (0.3/0.6 and 0.2/0.4 for fanout), minimum corner radius 0.25mm.
- Neckdown polygon generation attempted; persistent 3V3 neckdown collisions for U1/IC1/U3 were remediated by skipping those neckdowns after multiple attempts.
- Placement refined to preserve the intended floorplan zones (GNSS top-left, LoRa+SMA top-right, LTE+SMA bottom-right, MCU center, power+USB bottom-left/bottom edge) while reducing overlaps and improving routing channels; all components are now within the board outline.
- Latest DRC status still shows unresolved errors: overlapping copper remains (pads 68ec3f7c and b229b54f) and 44 unrouted connections (airwires).
Implementation plan
1. Re-run DRC to get current, precise overlap and airwire locations (do not rely on cached results) and identify which components/nets correspond to pads 68ec3f7c and b229b54f.
2. Clear remaining overlapping-copper errors by re-routing or adjusting local copper around the specific offending pads/nets (do not change board size or move RF connectors). Re-validate overlapping copper until zero.
3. Route power nets first (VBUS, VBAT/battery+charge path, 3V3) using width rules: 40 mil for battery/charge path, 20 mil for power distribution; prioritize short/wide paths in the power section and adequate via stitching for thermal/current return.
4. Route RF-critical traces second:
- Route LoRa RF from SX1262 matching network to LoRa SMA with no vias, no 90° bends, and maintain the CPWG geometry target; keep copper pours cleared under/around the RF feed as required.
- Route LTE RF to LTE SMA similarly with no vias and smooth bends.
- Add GND stitching via fences around RF keep-out regions at ~5mm pitch.
5. Route MCU-to-radio/control buses third:
- Route SX1262 SPI (SCK/MOSI/MISO/NSS) and control lines (BUSY/DIO1/NRESET) and ensure SPI length matching within 2mm.
- Route USB D+/D- from MCU to modem/USB-C as applicable with tight coupling and minimal stubs.
6. Route remaining audio, UI, and low-speed nets last, maintaining audio/RF isolation; ensure the NAU8810 analog ground island connection strategy is preserved.
7. Re-run full DRC and flag (and fix if possible): unconnected nets/airwires, RF keep-out violations, power trace width violations, and any new copper overlaps.
8. Run a decoupling audit: verify each IC has 100nF + 10uF where required and that caps are placed within 0.5mm of the associated power pins on the same layer; list any missing/too-far decouplers for manual correction.
Task completed.
1:00
- Board outline: 90 mm × 60 mm rectangle.
- Stackup:
- Layer 1: Top Signal
- Layer 2: Solid GND plane
- Layer 3: 3V3 Power plane
- Layer 4: Bottom Signal
- Do not resize the board.
- Do not move RF connectors/SMA placements unless required to fix a manufacturing blocker and explicitly documented.
- Preserve GNSS and RF keepout zones.
- Board setup has already been confirmed as 90 mm × 60 mm with a 4-layer stackup.
- L2 is assigned as Ground Plane.
- L3 is assigned as Power Plane.
- Baseline global layout rules have already been applied:
- Minimum trace width: 0.127 mm / 5 mil.
- Preferred widths: 0.127 mm / 0.508 mm / 1.016 mm for signal / power / battery-charge classes.
- Default via hole size: 0.3 mm.
- Via options noted: 0.3 / 0.6 mm standard and 0.2 / 0.4 mm for fanout.
- Minimum trace corner radius: 0.25 mm.
- Neckdown polygon generation was attempted.
- Persistent 3V3 neckdown collisions for U1 / IC1 / U3 were remediated by skipping those specific neckdowns after multiple attempts.
- Placement has been refined to preserve the floorplan:
- GNSS: top-left.
- LoRa + SMA: top-right.
- LTE + SMA: bottom-right.
- MCU: center.
- Power + USB: bottom-left / bottom edge.
- All components are currently within the board outline.
- Latest known unresolved DRC status:
- Overlapping copper remains around pads 68ec3f7c and b229b54f.
- 44 unrouted connections / airwires remain.
- Airwires / unrouted connections.
- Overlapping copper.
- Dangling traces.
- Floating copper.
- Invalid layers.
- Protected/keepout intrusions where available.
- Missing footprints.
- Under-connected vias.
- Current airwire count and affected nets/components.
- Current overlapping-copper count and exact pads/nets/components, especially pads 68ec3f7c and b229b54f.
- Whether any stale/dangling traces exist before routing.
- Do not change board size.
- Do not move RF connectors/SMA placements.
- Preserve RF/GNSS zones and keepouts.
- Prefer local routing/copper adjustment or moving small passives over moving major ICs/modules.
- Re-run overlapping-copper DRC until overlapping copper is zero, or list each remaining overlap with blocker reason.
- Check for dangling traces.
- Remove/clean stale dangling routing if present.
- Confirm stackup is still 4-layer with L2 GND and L3 Power.
- Confirm all components remain inside the 90 mm × 60 mm outline.
- VBUS.
- VBAT / battery path.
- Charger path.
- 3V3 distribution.
- 1V8 distribution if still unrouted.
- Battery / charge path: 1.016 mm / 40 mil.
- Main power distribution: 0.508 mm / 20 mil.
- Signal minimum: 0.127 mm / 5 mil.
- Keep power paths short and wide in the bottom-left power/USB section.
- Use multiple vias where power transitions layers.
- Preserve L2 as a continuous GND return plane.
- Preserve L3 as the 3V3 plane.
- Add/maintain thermal/current return via stitching around charger/regulator thermal pads and inductor ground-return regions.
- Route SX1262 / matching network to LoRa SMA.
- No vias in the RF feed path.
- No 90-degree bends; use 45-degree or smooth bends.
- Maintain intended CPWG geometry target where possible.
- Keep copper pours cleared under and around the RF feed as required.
- Preserve LoRa SMA placement and top-right RF floorplan.
- Route LTE modem RF path to LTE SMA.
- No vias in the RF feed path.
- No 90-degree bends; use 45-degree or smooth bends.
- Preserve LTE SMA placement and bottom-right floorplan.
- Preserve RF and GNSS keepouts.
- Add/maintain GND stitching via fences around RF keepout regions at approximately 5 mm pitch where supported.
- Do not allow copper under GNSS antenna keepout regions on any layer.
- SPI: SCK, MOSI, MISO, NSS.
- Control: BUSY, DIO1 IRQ, NRESET.
- Keep SPI length matching within 2 mm where practical.
- Route against the continuous L2 GND reference.
- Route USB D+ / D− from MCU to modem/USB-C as applicable.
- Keep D+ / D− tightly coupled, similar length, and with minimal stubs.
- Avoid crossing plane discontinuities.
- Audio codec / mic / speaker amp signals.
- UI buttons.
- RGB LED channels.
- UARTs, GPIOs, status lines, reset lines, and remaining low-speed control.
- Maintain separation between audio and RF sections.
- Preserve NAU8810 analog-ground strategy: analog ground island tied to digital ground at a single controlled point under/near NAU8810 where the design implements this topology.
- Airwires / unrouted nets.
- Overlapping copper.
- Floating copper.
- Dangling traces.
- Invalid layer assignments.
- Protected/keepout intrusions.
- RF keepout violations.
- Power trace width violations.
- Under-connected vias.
- Missing footprints.
- Remaining airwire count and list of affected nets/components.
- Remaining copper overlap count and affected geometry/components.
- RF/GNSS keepout status.
- Power-width compliance status for VBUS, VBAT/charge, 3V3, and 1V8.
- Any issues that require manual RF tuning or manual PCB editor intervention.
- Every IC power pin should have local 100 nF decoupling where required.
- Each IC power domain should have appropriate local/bulk 10 uF capacitance where required.
- Decoupling capacitors should be on the same layer as the IC where practical.
- Target placement distance: within 0.5 mm of the associated IC power pin when feasible.
- Missing 100 nF capacitors.
- Missing 10 uF bulk/local capacitors.
- Capacitors placed farther than 0.5 mm from their associated power pins.
- Any caps that require manual relocation.
- Board remains 90 mm × 60 mm.
- Stackup remains Top Signal / L2 GND / L3 3V3 Power / Bottom Signal.
- RF/GNSS keepouts and SMA placements are preserved.
- Overlapping copper is reduced to zero, or every remaining overlap is explicitly documented with a blocker reason.
- Airwires are reduced as far as possible, with all remaining unrouted nets listed.
- Power routing follows 40 mil battery/charge and 20 mil power distribution targets.
- RF paths avoid vias and 90-degree bends.
- SPI to SX1262 is length-matched within 2 mm where practical.
- DRC/review results are refreshed after the routing pass.
- Missing or poorly placed decoupling is documented for correction.
- Follow the DRC fix priority: missing footprints, invalid layers, overlapping copper, clearance/protected intrusions, dangling traces, floating copper, airwires, then ERC-quality issues.
- Do not route before clearing manufacturing-blocking overlaps and dangling traces.
- If routing remains blocked, diagnose whether the cause is congestion, local overlap, keepout restriction, or unroutable fanout, then move only the smallest non-critical component necessary while preserving RF connector positions.
Objective
Board and Stackup Requirements
Current Known State
Execution Sequence
1. Fresh DRC Snapshot
2. Clear Copper Overlaps First
3. Pre-Routing Cleanup
4. Route Power Nets First
5. Route RF-Critical Traces Second
6. Route MCU-to-Radio and Control Buses Third
7. Route Remaining Low-Speed Nets Last
8. Final DRC / Review Pass
9. Decoupling Audit
Success Criteria
Notes for Execution
