Designing PeakNode 1 Specifications

Started implementing a plan

Create an updated brief to execute the PeakNode 1 PCB routing pass on a 90×60mm 4-layer board (Top Signal / L2 GND solid / L3 3V3 Power plane / Bottom Signal), preserving RF/GNSS keepouts and SMA placements, and then run DRC to flag airwires, copper overlaps, RF keepout violations, power width violations, and missing decoupling.

What has been done so far

- Confirmed board setup: 90mm × 60mm rectangle and 4-layer stackup with L2 as Ground Plane and L3 as Power Plane.

- Applied baseline global layout rules: min trace width 0.127mm (5 mil), preferred widths 0.127mm/0.508mm/1.016mm (5/20/40 mil), hole size 0.3mm, via options noted (0.3/0.6 and 0.2/0.4 for fanout), minimum corner radius 0.25mm.

- Neckdown polygon generation attempted; persistent 3V3 neckdown collisions for U1/IC1/U3 were remediated by skipping those neckdowns after multiple attempts.

- Placement refined to preserve the intended floorplan zones (GNSS top-left, LoRa+SMA top-right, LTE+SMA bottom-right, MCU center, power+USB bottom-left/bottom edge) while reducing overlaps and improving routing channels; all components are now within the board outline.

- Latest DRC status still shows unresolved errors: overlapping copper remains (pads 68ec3f7c and b229b54f) and 44 unrouted connections (airwires).

Implementation plan

1. Re-run DRC to get current, precise overlap and airwire locations (do not rely on cached results) and identify which components/nets correspond to pads 68ec3f7c and b229b54f.

2. Clear remaining overlapping-copper errors by re-routing or adjusting local copper around the specific offending pads/nets (do not change board size or move RF connectors). Re-validate overlapping copper until zero.

3. Route power nets first (VBUS, VBAT/battery+charge path, 3V3) using width rules: 40 mil for battery/charge path, 20 mil for power distribution; prioritize short/wide paths in the power section and adequate via stitching for thermal/current return.

4. Route RF-critical traces second:

- Route LoRa RF from SX1262 matching network to LoRa SMA with no vias, no 90° bends, and maintain the CPWG geometry target; keep copper pours cleared under/around the RF feed as required.

- Route LTE RF to LTE SMA similarly with no vias and smooth bends.

- Add GND stitching via fences around RF keep-out regions at ~5mm pitch.

5. Route MCU-to-radio/control buses third:

- Route SX1262 SPI (SCK/MOSI/MISO/NSS) and control lines (BUSY/DIO1/NRESET) and ensure SPI length matching within 2mm.

- Route USB D+/D- from MCU to modem/USB-C as applicable with tight coupling and minimal stubs.

6. Route remaining audio, UI, and low-speed nets last, maintaining audio/RF isolation; ensure the NAU8810 analog ground island connection strategy is preserved.

7. Re-run full DRC and flag (and fix if possible): unconnected nets/airwires, RF keep-out violations, power trace width violations, and any new copper overlaps.

8. Run a decoupling audit: verify each IC has 100nF + 10uF where required and that caps are placed within 0.5mm of the associated power pins on the same layer; list any missing/too-far decouplers for manual correction.

Task completed.

1:00

Thought for 6 sec — Retrieving skills information
Accessing knowledge.

flux

Created the updated routing execution brief for PeakNode 1 and saved it as PeakNode 1 PCB Routing Pass Brief. It captures the 90×60 mm 4-layer stackup, current DRC state, routing order, RF/GNSS/SMA preservation requirements, DRC checklist, and decoupling audit criteria.
mkommar

mkommar

After routing, re-run checks for airwires, copper overlaps, RF keepout infringement, power-width mismatches, and decoupling placement

flux

I re-ran the checks: the board is not clean yet — current results show 32 airwire errors, 6 overlapping-copper errors, 1 floating-copper error, and 21 dangling-trace warnings. No specific RF-keepout or power-width violation was returned by the checked DRC set, and no decoupling error/warning was returned, but the 0.5 mm same-layer decoupling requirement still needs physical placement inspection; details are saved in Post-Routing DRC Checks.
Fix routing errors
Locate airwires
Check decoupling placement
Check power widths
Document fixes
Sign up to send
U3 VDDD - U3 VDDSPK
J1 VBUS__1 - IC3 VINx
IC1 PA9 - U1 RXD
U1 V_IO - U3 VDDA
IC1 PA10 - U1 TXD
IC1 PB3 - J4 6
IC1 PA13 - J4 2
IC1 NRST - J4 10
IC3 ISO_Bx - U5 1
U3 VDDD - U3 VDDSPK
IC1 PA14 - J4 4
IC3 EP - U4 GND
J4
U3 VSSD - U3 VSSSPK
U3 VSSD - U3 VSSSPK
GND
U2 GND_2 - U2 GND_3
U1 GND__8 - U2 GND_1
IC2 GND_23 - U1 GND
U2 GND_2 - U2 GND_3
J4 9 - C1 P2
U3 VSSD - U3 VSSSPK
U1 GND__8 - U2 GND_1
IC3 EP - U4 GND
U2 GND_5 - U3 VSSA
U2
U5
U1
J1
U3

PeakNode 1

PeakNode 1 thumbnail
Ruggedized battery-powered PeakNode 1 LoRa PWAN node with SX1262 LoRa mesh over SPI, LTE Cat-M1/NB-IoT modem, GNSS, LPCNet-capable audio path, USB-C charging and LiFePO4 power management. Targets a 4-layer 90 mm x 60 mm IPC Class 2 layout with 3.3 V main and 1.8 V I/O rails, dual SMA antennas, two RGB status LEDs, three tactile buttons, low-leakage power architecture for sub-10 uA sleep, and defined RF keep-out zones under the LoRa and LTE antenna regions.

Properties

3.3V main, 1.8V IO

Mouser, Digi-Key, LCSC alternate

4-layer 90x60mm board with RF keep-out zones under SX1262 and LTE antenna regions; dual SMA connectors; LoRa SPI, LTE UART/USB, GNSS UART, audio codec path, two RGB LEDs, three buttons

2 RGB LEDs, 3 tactile buttons, audio I/O

1-cell LiFePO4 input, USB-C charging, 3.3V main rail, 1.8V LTE/modem IO target, sleep current under 10uA

-40C to 85C

IPC Class 2 rugged field node

LoRa mesh, LTE Cat-M1/NB-IoT, GNSS

Pricing & Availability

Distributor

Qty 1

Arrow

$43.64–$47.41

Digi-Key

$67.78–$87.35

LCSC

$116.56

Mouser

$66.56

TME

$2.26

Verical

$33.88–$44.34

Controls