Relay Board Schematic Design
Thought for 4 sec
Here’s the schematic plan I’d use for the separate 10-channel 220 VAC relay board.
High-level architecture
Schematic blocks to create 1. AC mains inputText
Control board harness 10x coil drive signals │ ▼ Relay coil interface / flyback protection │ ▼ 10x 24 VDC relay coils AC mains input L / N / PE │ ▼ Main protection ~50 A │ ▼ AC live bus │ ├── CH1 fuse 15 A ─ relay contact ─ output terminal CH1 ├── CH2 fuse 15 A ─ relay contact ─ output terminal CH2 ├── ... └── CH10 fuse 15 A ─ relay contact ─ output terminal CH10 Neutral and protective earth distributed to all output terminals
Use a high-current terminal block for:
AC_L_INAC_N_INPE_IN
For 220 VAC and high current, I would keep this as a physically separated high-voltage section with clear labeling and wide spacing.
2. Main input protection
Add one main protection device before the per-channel distribution.
Recommended options:
- Panel-mount / chassis-mount breaker or fuse, not PCB-only, for ~50 A mains input.
- If represented on the PCB schematic, use a connector or symbol for an external 50 A breaker/fuse.
- Do not rely on a small PCB fuse holder for 50 A mains protection.
Suggested net flow:
3. Ten relay output channelsText
AC_L_IN → MAIN_FUSE_OR_BREAKER → AC_L_PROTECTED AC_N_IN → AC_N_BUS PE_IN → PE_BUS
Each channel should have:
- HANKUK
HR85AKS-DC24relay - Replaceable 15 A fuse on the live output path
- AC output terminal, preferably 3-pin:
- switched live
- neutral
- protective earth
Recommended per-channel topology:
Text
AC_L_PROTECTED → CHx_FUSE_15A → relay COM relay NO → CHx_L_OUT AC_N_BUS → CHx_N_OUT PE_BUS → CHx_PE_OUT
I’d use the relay in normally-open mode unless you explicitly need fail-on behavior.
4. 24 V relay coil power input
Add a low-voltage power connector:
Text
+24V_COIL_IN 0V_COIL_IN
Then distribute:
Text
+24V_COIL → one side of all relay coils coil low side → harness drive signal / transistor driver return path
Important question: are the 10 incoming control signals already low-side coil drivers, or are they just ESP32/logic-level signals?
- If they are already ULN2803/open-drain low-side outputs from the control board, this relay board only needs coil connections and flyback handling.
- If they are logic-level signals, this relay board needs transistor/MOSFET/ULN2803 drivers.
Use a harness connector with at least:
COIL_DRV_1COIL_DRV_2- …
COIL_DRV_100V_COIL- optional
+24V_COILif coil power is also delivered through the harness - optional spare / key / detect pin
For reliability, I’d prefer the 24 V coil supply on a separate higher-current connector, not the signal harness, unless the harness is sized for relay coil current.
6. Coil flyback protection
Each 24 V relay coil needs suppression.
Options:
- Diode across each coil: simple, low-cost, slower relay release.
- TVS or diode + Zener: faster release, better for relay contact timing.
- If the control board already has ULN2803A, note that ULN2803 includes clamp diodes, but the relay board still needs the correct
COMclamp connection to+24V.
For a separate relay board, I’d put local flyback diodes or TVS protection on the relay board so protection stays close to the coils.
Safety/layout constraints to carry into the schematic
- Keep low-voltage harness/24 V coil section physically isolated from 220 VAC contact/output section.
- Use large creepage/clearance between:
- AC live/neutral/PE and low-voltage control
- relay contact pins and coil pins
- adjacent high-current channels
- Use wide copper or copper pours for 15 A paths.
- Consider using slots/cutouts between relay coil/control pins and contact pins.
- Label all high-voltage nets clearly.
- Prefer external/chassis wiring for the full 50 A main feed if PCB copper thickness/width cannot safely support it.
- Are the incoming 10 control signals logic-level inputs or already coil-driver low-side outputs?
- Should each output socket switch live only, or live and neutral?
- Should the board include current sensing or status feedback per channel?
- What connector style/current rating do you want for the AC input and outputs?
- Will the 50 A main protection be on-board, panel-mounted, or external?
My recommended starting schematic is: external/main 50 A breaker → live bus → 10× 15 A fused normally-open relay channels, with neutral and PE distributed directly to each output, and local flyback suppression for all 24 V relay coils.
Use low-side drivers
Add relay drivers
Switch live only
Specify connectors
Create schematic plan
Refine this doc
Ask about this doc
Low-Voltage Control Section Notes
Scope built
This first schematic stage intentionally includes only the low-voltage control section:
- 24 V DC input connector from an external SMPS.
- 24 V to 5 V buck module.
- 5 V to 3.3 V AMS1117 regulator.
- ESP32 DevKit controller.
- Two 74HC595 output shift registers.
- Two 74HC165 input shift registers.
- I2C OLED display.
- Ten channel status LEDs with 470 Ω series resistors.
- Ten DPDT latching manual override/readback switches and four setup/menu tactile buttons on the 74HC165 input chain.
- Two ULN2803A low-side relay-driver arrays.
- Ten 2N2222 manual override low-side relay-driver transistors with 1 kΩ base resistors.
- Twenty 1N4148 diode-OR isolation diodes between MCU and manual relay sink paths.
- Ten low-voltage relay-coil output connectors.
- Isolated PT secondary mains-voltage sensing front end into ESP32 GPIO36.
- Bulk and decoupling capacitors.
The AC mains relay/contact section, fuse holders, and mains output terminals are intentionally not built yet. The PT primary/mains side must remain off-board or in the later mains section with proper creepage/clearance; this stage only accepts the isolated PT secondary.
Power architecture
Table
| Net | Source | Loads / Notes |
|---|---|---|
24V_IN | J1 external 24 V SMPS input | Feeds MP1584 buck module only in this stage |
24V_RELAY | J2–J11 relay coil connectors / external 24 V relay supply | Positive relay coil rail; tied to U8/U9 COM pins for ULN2803 flyback clamp diodes |
5V | U1 MP1584EN module output | Feeds U2 AMS1117 input and manual override base-drive switch poles |
3V3 | U2 AMS1117-3.3 output | ESP32 DevKit 3V3 pin, 74HC595/74HC165 VCC, OLED VCC pin, LED drive logic, input pull-ups |
GND | J1 input return | Common low-voltage control ground |
Power budget assumptions for this stage
Approximate low-voltage control loads:
Table
| Load | Rail | Estimate |
|---|---|---|
| ESP32 Wi-Fi peak | 3.3 V | 500 mA peak allowance |
| 74HC595 ×2 + 74HC165 ×2 | 3.3 V | <20 mA typical logic current excluding loads |
| OLED display | 3.3 V | 20–30 mA typical module estimate |
| 10 status LEDs | 3.3 V | about 2–3 mA each with 470 Ω resistors, ~25 mA total |
| 14 input pull-ups | 3.3 V | 10 kΩ each; worst case all pressed ≈4.6 mA total |
| Manual override base drive | 5 V | 10 × 1 kΩ base resistors; worst-case all manual channels active ≈43 mA from 5 V |
| Relay coils | 24 V | Not yet specified; size 24V_RELAY, J2–J11, U8/U9/manual transistor current, and power input once relay coil current is selected |
Design allowance used on the schematic: approximately 0.6 A peak on the 3.3 V rail. Relay coil current is not included because the relay part/coil current has not been selected yet.
Thermal note: AMS1117 dissipates
(5 V - 3.3 V) × I_3V3. At 0.6 A peak this is about 1.0 W, which is high for small linear regulators. For a production board, consider powering the ESP32 DevKit from a high-efficiency 3.3 V buck regulator or reducing the 3.3 V load through the AMS1117.Signal mapping
Table
| Function | ESP32 pin | Net | Connected to |
|---|---|---|---|
| 74HC595 data | GPIO23 | SR595_DATA | U4 SER |
| 74HC595 shift clock | GPIO18 | SR595_CLK | U4/U5 SRCLK |
| 74HC595 latch | GPIO5 | SR595_LATCH | U4/U5 RCLK |
| 74HC165 serial data | GPIO19 | SR165_DATA | U6 Q7 |
| 74HC165 clock | GPIO22 | SR165_CLK | U6/U7 CP |
| 74HC165 load | GPIO21 | SR165_LOAD | U6/U7 ~PL |
| OLED SDA | GPIO26 | I2C_SDA | OLED SDA + 4.7 kΩ pull-up |
| OLED SCL | GPIO27 | I2C_SCL | OLED SCL + 4.7 kΩ pull-up |
| Isolated PT voltage sense | GPIO36 / ADC1 | MAINS_VSENSE_ADC | Rectified/filtered/scaled PT secondary voltage |
Intentional deviation from uploaded BOM
The uploaded BOM assigned OLED I2C to GPIO16/GPIO17. The selected ESP32 DevKit library symbol does not expose GPIO16/GPIO17 terminals, so the OLED was routed to GPIO26/GPIO27 instead. Firmware must use
Wire.begin(26, 27) unless the ESP32 component is later replaced with a variant exposing GPIO16/GPIO17.Output shift-register allocation
Table
| Channel | 74HC595 output | LED path |
|---|---|---|
| 1 | U4 QA | R1 + D1 |
| 2 | U4 QB | R2 + LED1 |
| 3 | U4 QC | R3 + LED2 |
| 4 | U4 QD | R4 + LED3 |
| 5 | U4 QE | R5 + LED4 |
| 6 | U4 QF | R6 + LED5 |
| 7 | U4 QG | R7 + LED6 |
| 8 | U4 QH | R8 + LED7 |
| 9 | U5 QA | R9 + LED8 |
| 10 | U5 QB | R10 + LED9 |
Unused U5 outputs are marked no-connect for this stage.
Relay-driver allocation
U8 and U9 are ULN2803A Darlington low-side driver arrays. Each 74HC595 channel output net drives both its status LED resistor and the corresponding ULN2803 input. Relay coil connectors are low-voltage coil connections only: pin 1 is
24V_RELAY, pin 2 is the shared relay coil low node. U8/U9 COM pins are tied to 24V_RELAY so the internal clamp diodes can absorb relay coil flyback energy.Each relay coil low node is diode-OR isolated between two sink paths:
- MCU path: relay coil low node → 1N4148 → ULN2803 output.
- Manual path: relay coil low node → 1N4148 → 2N2222 collector; 2N2222 emitter to
GND; base driven from5Vthrough a DPDT latching switch pole and a 1 kΩ resistor.
This keeps the 74HC595/ULN2803 path and manual transistor path isolated while either path can energize the same relay coil.
| Channel | 74HC595 control net | ULN input | ULN isolated sink | Manual transistor | Relay coil connector |
|---:|---|---|---|---|
| 1 |
CH1_LED_DRV | U8 I1 | CH1_ULN_ISO_SINK via D8 | Q1 via D9/R27/SW10 | J2 pin 2 / CH1_RELAY_SINK |
| 2 | CH2_LED_DRV | U8 I2 | CH2_ULN_ISO_SINK via D10 | Q2 via D11/R28/SW11 | J3 pin 2 / CH2_RELAY_SINK |
| 3 | CH3_LED_DRV | U8 I3 | CH3_ULN_ISO_SINK via D12 | Q3 via D13/R29/SW12 | J4 pin 2 / CH3_RELAY_SINK |
| 4 | CH4_LED_DRV | U8 I4 | CH4_ULN_ISO_SINK via D14 | Q4 via D15/R30/SW13 | J5 pin 2 / CH4_RELAY_SINK |
| 5 | CH5_LED_DRV | U8 I5 | CH5_ULN_ISO_SINK via D16 | Q5 via D17/R31/SW14 | J6 pin 2 / CH5_RELAY_SINK |
| 6 | CH6_LED_DRV | U8 I6 | CH6_ULN_ISO_SINK via D18 | Q6 via D19/R32/SW15 | J7 pin 2 / CH6_RELAY_SINK |
| 7 | CH7_LED_DRV | U8 I7 | CH7_ULN_ISO_SINK via D20 | Q8 via D21/R33/SW16 | J8 pin 2 / CH7_RELAY_SINK |
| 8 | CH8_LED_DRV | U8 I8 | CH8_ULN_ISO_SINK via D22 | Q9 via D23/R34/SW17 | J9 pin 2 / CH8_RELAY_SINK |
| 9 | CH9_LED_DRV | U9 I1 | CH9_ULN_ISO_SINK via D24 | Q10 via D25/R35/SW18 | J10 pin 2 / CH9_RELAY_SINK |
| 10 | CH10_LED_DRV | U9 I2 | CH10_ULN_ISO_SINK via D26 | Q11 via D27/R36/SW19 | J11 pin 2 / CH10_RELAY_SINK |U9 channels 3–8 are unused and intentionally marked no-connect.
Isolated PT mains-voltage sensing
J12 accepts only the isolated potential-transformer secondary. The PT primary must connect to the 220 V mains side outside this low-voltage section and must maintain mains creepage/clearance from the low-voltage control PCB area.
Assumption used for this first implementation: 6 VAC nominal PT secondary at 220 VAC primary. The sensing chain is:
J12 PT secondary → D28–D31 bridge rectifier → C13 10 µF filter → R37/R38 divider → R39 10 kΩ series resistor → GPIO36 ADCTable
| Function | Components / Nets |
|---|---|
| PT secondary input | J12, PT_SEC_A, PT_SEC_B |
| Bridge rectifier | D28, D29, D30, D31 |
| Rectified/filter node | PT_RECT_POS, C13 10 µF to GND |
| Divider | R37 = 100 kΩ high side, R38 = 33 kΩ low side |
| ADC protection/filter | R39 = 10 kΩ series, C14 = 100 nF to GND, D32 clamp to 3V3, D33 clamp to GND |
| ESP32 ADC | U3 GPIO36 / MAINS_VSENSE_ADC |
Firmware must calibrate the displayed mains voltage against a known safe reference because PT ratio, diode drops, capacitor loading, ADC nonlinearity, and mains frequency affect the measured DC value. If a different PT secondary voltage is selected, recalculate R37/R38 so
MAINS_VSENSE_ADC remains below 3.3 V under high-line conditions.Input shift-register allocation
All U6/U7 parallel inputs are active-low: each net has a 10 kΩ pull-up to
3V3, and the switch/button contact shorts the input to GND when active.Table
| Function | Net | 74HC165 input | Pull-up | Switch/button |
|---|---|---|---|---|
| Channel 1 readback | CH1_READBACK_N | U6 D0 | R13 | SW10 pole A |
| Channel 2 readback | CH2_READBACK_N | U6 D1 | R14 | SW11 pole A |
| Channel 3 readback | CH3_READBACK_N | U6 D2 | R15 | SW12 pole A |
| Channel 4 readback | CH4_READBACK_N | U6 D3 | R16 | SW13 pole A |
| Channel 5 readback | CH5_READBACK_N | U6 D4 | R17 | SW14 pole A |
| Channel 6 readback | CH6_READBACK_N | U6 D5 | R18 | SW15 pole A |
| Channel 7 readback | CH7_READBACK_N | U6 D6 | R19 | SW16 pole A |
| Channel 8 readback | CH8_READBACK_N | U6 D7 | R20 | SW17 pole A |
| Channel 9 readback | CH9_READBACK_N | U7 D0 | R21 | SW18 pole A |
| Channel 10 readback | CH10_READBACK_N | U7 D1 | R22 | SW19 pole A |
| Setup/Menu | BTN_MENU_N | U7 D2 | R23 | S2 |
| Setup/Up | BTN_UP_N | U7 D3 | R24 | S3 |
| Setup/Down | BTN_DOWN_N | U7 D4 | R25 | S4 |
| Setup/Enter | BTN_ENTER_N | U7 D5 | R26 | S5 |
U7 D6/D7 are still unused for this stage and should be tied or no-connected intentionally if ERC flags them later.
Open items before the next schematic stage
- Replace or confirm the ESP32 DevKit part if GPIO16/GPIO17 must be preserved exactly.
- Confirm the actual PT part, secondary voltage, isolation rating, and calibration factor before layout/production.
- Select the actual 24 V relay/contactor coil current and confirm U8/U9, 2N2222 transistors, diode current, connectors, trace width, and input supply current margin.
- Revisit the 3.3 V regulator thermal design before layout or production.
- Decide whether unused U7 D6/D7 should be tied to a fixed logic level for production robustness.
Scope built
Power architecture
Power budget assumptions for this stage
Signal mapping
Intentional deviation from uploaded BOM
Output shift-register allocation
Relay-driver allocation
Isolated PT mains-voltage sensing
Input shift-register allocation
Open items before the next schematic stage
