Gas Sampling Pump PCB Design
Yes, create a separate pump project and start the full schematic there.
Thought for 3 sec
I’ll create a separate pump project, then start schematic capture there so the existing NH3 transmitter stays intact.
Worked for 39 sec
The new project is created: /mikaelle/gas-sampling-pump-pcb-design. I’ve started a dedicated schematic-capture thread there and will wait for its result before continuing verification/layout.
Worked for 4 mins 51 sec
Created the separate project and started schematic capture there: /mikaelle/gas-sampling-pump-pcb-design
Open items:
- The schematic-capture thread is still running in the new project.
- Layout/routing will wait until schematic/ERC is complete.
Suggested next steps:
- Open the new project to watch progress.
- Once schematic capture completes, ask me to review/fix ERC and continue to PCB layout.
Review then layout
Check schematic status
Run ERC fixes
Explain pump protection
Optimize for manufacturing
Refine this doc
Ask about this doc
Layout Placement Notes — Analog NH3 Loop Transmitter
What Was Changed
- Board resized from the default 160 × 100 mm to an 80 × 60 mm compact industrial outline with 2 mm rounded corners.
- Stackup kept as 4 layers and configured with an internal ground-plane priority to improve analog return paths and EMI performance.
- Components were re-placed by functional block:
- Left edge: sensor connector J2 and low-noise AFE.
- Left/quiet analog region: U2 LMP7721 TIA, U3 potentiostat, R7/R8/R9/R10/R11, RV1, C11, C12.
- Center: reference and analog signal conditioning, including U5, U4, RV2, and precision resistor/filter network.
- Right edge: loop connector J1.
- Right/power region: loop protection, LDO, current sink, Q1, R12/R13/R14, and input filtering.
- Added a silkscreen dashed rectangle and label around the WE/TIA region:
VCM GUARD: route around WE / U2 IN-.
Guard Strategy
The high-impedance WE summing node is intentionally placed in a quiet left-side region. R8 and the TIA feedback network are close to U2 so the WE trace can be kept very short.
Important: I did not add a floating copper guard pour, because a copper shape not tied to VCM would create a floating-copper/DFM issue. The correct implementation during routing is:
- Route J2 Pin_1 -> R8 -> U2 IN- as the shortest possible top-layer trace.
- Route a VCM_1V25 guard trace/ring around the WE/TIA summing node and around U2 IN- / R8 / C11 / RV1.
- Keep the guard on the same layer as the WE trace where possible.
- Avoid vias on WE unless absolutely unavoidable.
- Keep RAW_LOOP_PLUS, LOOP_PLUS, MOS_GATE, Q1, and TVS/current-sink copper away from the guard/WE area.
Placement Review
- Placement completed with all components in-bounds and no component overlap reported by the placement engine.
- Sensor/AFE and power/current-sink blocks are physically separated across the board.
- Q1 was placed on the right-side power region with open surrounding board area for copper heat spreading.
- J1 and J2 are on opposite board edges, improving separation between field loop wiring and sensor wiring.
Routing Attempt — 2026-05-19
- The available router was run after the user requested routing of the WE guard in VCM_1V25.
- It completed successfully and added 397 routing nodes.
- The router available in this session is the global auto-router, not a manual single-net guard-ring router. Therefore it can connect the VCM_1V25 net but cannot guarantee a true driven guard ring geometry around U2 IN-.
- A visual/manual pass is still required to confirm the guard ring shape and, if necessary, draw the VCM_1V25 guard trace manually around U2 IN-.
EP Pad Overlap Status
- U3/U4 still report overlapping copper at EP against internal footprint mount pads.
- Attempts were made to deactivate or remove the redundant internal mount pads, but the layout editor did not accept those internal node edits by UID/selector in this session.
- The overlap appears to be caused by footprint-internal mount pads overlapping the real exposed pad, not by component placement overlap.
- This remains a manufacturing-blocking issue unless verified as same-net intentional copper or fixed by editing/replacing the footprint.
Current Review Status
- Remaining issues include unresolved U3/U4 EP internal footprint overlap.
- Airwire status after auto-routing should be checked before manufacturing export.
- Do not fabricate/export manufacturing files until routing and final DRC are clean.
Next Routing / Cleanup Requirements
- Verify the VCM_1V25 path near U2 visually; create/adjust a true guard ring around U2 IN- if the auto-router did not produce one.
- Resolve U3/U4 EP footprint-internal overlap by footprint edit/replacement or verified same-net acceptance.
- Re-run DRC for airwires, overlapping copper, dangling traces, and clearance.
- Only then proceed to manufacturing export.
What Was Changed
Guard Strategy
Placement Review
Routing Attempt — 2026-05-19
EP Pad Overlap Status
Current Review Status
Next Routing / Cleanup Requirements
