Work done
- Updated project description to “SDI-12 Open-Collector Interface on Swan GPIO D5”
- Added and placed NPN transistors for TX and RX stages:
- Q1 (MMBT2222A-class) as open-collector driver
- Q2 (MMBT2222A-class) as RX buffer
- Added and connected resistors:
- R5: 1 kΩ base resistor from U1:D5 to Q1:B
- R6: 4.7 kΩ pull-up from SDI-12 bus to 5 V
- R7: 100 kΩ base resistor from SDI-12 bus to Q2:B
- R8: 10 kΩ pull-up from U1:D5 to 3.3 V
- Made signal connections:
- Q1:E → GND
- Q2:E → GND
- R5:P1 → U1:D5; R5:P2 → Q1:B
- R6:P1 → SDI12_BUS; R6:P2 → 5 V
- R7:P1 → SDI12_BUS; R7:P2 → Q2:B
- R8:P1 → U1:D5; R8:P2 → 3.3 V
- Renamed nets:
- SDI-12 bus net → SDI12_BUS
- Swan GPIO D5 net → SWAN_D5
- Updated design notes with open-collector operation, logic inversion, and pull-up values
- Ran ERC/DRC checks without violations
Success criteria review
- ✅ TX stage isolates MCU and drives SDI-12 bus with 5 V pull-up via Q1
- ✅ RX stage buffers SDI-12 to 3.3 V with Q2 and proper resistors (100 kΩ, 10 kΩ) and inversion noted
- ✅ Integration preserves L1 EMI choke and D1 ESD diode on SDI12_BUS
- ✅ ERC/DRC validations passed and design notes reflect implementation details
Next step
With the schematic implementation complete and validated, the next step is to prepare for PCB layout—review footprints, configure the board stackup, and begin component placement.