Project Overview and Analysis

flux

6:09

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Here’s a concise, engineering-focused walkthrough of this project.
Purpose and high-level concept
  • Goal: Environmental radiation logger that senses ionizing events via a photodiode analog front end, timestamps them, and stores data to removable media.
  • Core functions:
    • Sense: Analog front-end with high-speed op amps on ±6 V rails.
    • Compute/control: MCU manages acquisition, timestamping, storage, and I/O.
    • Timekeeping: RTC for accurate timestamps.
    • Storage: microSD over SPI.
    • I/O/Debug: Pin headers for power, control, and UART.
Core components and roles
  • Compute:
    • U3 STM32F030C6T6 – 32-bit MCU. SPI connects to microSD, I2C connects to RTC, UART to header.
  • Timekeeping:
    • IC1 DS3231M+ – I2C RTC. VCC and VBAT currently tied to 3.3 V rail net.
  • Storage:
    • U4 ST-TF-003A – microSD socket. Wired to SPI signals from MCU.
  • Sensor and analog front end:
    • Photodiode: CELL1 BPW34 – radiation-induced charge converted to voltage/current signal.
    • Gain/conditioning: U5, U6 OPA847IDBVTG4 – high-speed op-amp stages running on ±6 V.
    • Bias/feedback network: R1, R2, RIN1, RIN2, RF1, RF2, C5, C6.
  • Decoupling and support:
    • C1, C2, C3, C4, C7, C8, C9, C10 – decoupling/bulk caps on 3.3 V and possibly analog rails (values not yet specified).
  • Headers/IO:
    • J1 Pin Header 01x06 – brings out nets including the analog front end.
    • J2 Pin Header 01x06 – UART header with power and GND.
  • Power rails in use: +3V3 net for digital, +6V and -6V nets for op-amps (generation circuitry is implied by portals but not in this schematic).
How the blocks interact (key nets)
  • MCU to RTC over I2C: U3 PB10/PB11 connect to IC1 SCL/SDA (nets “Net (U3 - PB10)”, “Net (U3 - PB11)”).
  • MCU to microSD over SPI: U3 PA4/PA5/PA6/PA7 to U4 CS/SCK/DO/DI.
  • Time base and reset: U3 NRST is broken out with C9 (check for a pull-up).
  • Analog path: Photodiode CELL1 node biases via R1/R2 and couples into U5; the second stage U6 further conditions the signal. Output is exposed as “GAMMA_RAW” into MCU U3 PB0.
  • Power: +3V3 powers MCU/RTC/SD; +6V/-6V power the op-amp stages. Power generation and monitoring are hinted (e.g., +6V_BUCK_EN, _PG, _V_MON, _I_MON, -6V_CHRG_PUMP_EN), but the actual regulators/charge pump parts are not yet placed.
Key technologies, dependencies, and design choices
  • Interfaces
    • I2C requires pull-ups on SDA/SCL. Best practice: include pull-ups and size them to meet the rise-time spec. For 100 kHz mode, use a maximum rise time of 1000 ns; for 400 kHz, 300 ns. Default recommendation: add two 4.7k Resistor pull-ups to 3.3 V (tune vs bus capacitance, 400 pF max).
    • SPI to microSD: add series termination resistors of 22–33 Ω on SCK/MOSI/MISO/CS to damp edges and reduce ringing. Suggest four 22Ω Resistor near the MCU pins.
    • UART header is provided on J2 for debugging.
  • Power and grounding
    • Mixed-signal layout needs careful ground plane management so analog return currents (from op-amps) do not share digital return paths and inject noise.
    • Decoupling: Use a local combo per IC to cover wide frequencies: 100nF Capacitor at each VCC/VSS within 5 mm, plus 1uF Capacitor and 10uF Capacitor nearby as bulk. Operate capacitors at no more than 60% of their rated voltage; place the smallest value closest to the pin. Ensure negative rail (−6 V) decoupling near U5/U6.
  • RTC backup
    • IC1 VBAT is on the 3.3 V rail now; for timekeeping during main power loss, add a backup cell (e.g., Coin Cell Holder) or Supercapacitor with appropriate isolation from 3.3 V.
Design breakdown and implementation status
  • Digital domain is largely connected and coherent (MCU, SPI, I2C, UART).
  • Analog front end is present but will need value selection for RIN1/RIN2/RF1/RF2/C5/C6 for stability and target bandwidth/noise.
  • Power subsystem is not yet implemented: ±6 V rails and monitors are referenced but regulator/charge-pump parts are absent.
Trade-offs and optimizations
  • MCU: U3 is resource-light and low cost; adequate for SPI/I2C logging but SPI microSD will be slower than SDIO. Simplicity over peak throughput.
  • RTC: IC1 gives accurate timekeeping with minimal BOM and firmware overhead; backup supply is a design choice affecting data continuity during outages.
  • Analog: U5/U6 on ±6 V maximize headroom and linearity for fast pulses; cost and power are higher than single-supply op-amps. Dual-rail supply complicates power design but improves dynamic range.
  • Layout/EMI: Series terminations on SPI and disciplined decoupling reduce ringing/EMI; ground partitioning mitigates digital noise in the analog chain.
Potential challenges and performance considerations
  • Analog noise and stability: High-speed amplifiers are sensitive to layout parasitics. Ensure tight feedback loops, short decoupling paths on both +6 V and −6 V, and consider compensation caps in feedback if needed (e.g., C0G Capacitor for stability).
  • I2C reliability: Without SDA/SCL pull-ups the bus will not function; also verify bus rise times to meet 100 kHz/400 kHz modes and total bus capacitance ≤ 400 pF.
  • SPI integrity: Fast edges to microSD can ring without series resistors; add 22–33 Ω near the driver.
  • Power integrity: The ±6 V generation is not yet defined. You will need a +6 V rail (e.g., Buck Regulator) and an inverter for −6 V (e.g., Inverting Charge Pump or inverting regulator), each with proper input/output decoupling and grounding.
  • Reset robustness: MCUs should have a reset pull-up; confirm one is present for U3 NRST in addition to C9.
Real-world applications
  • Environmental radiation monitoring for labs, field surveys, and educational kits.
  • Long-term logging with timestamped event counts or pulse height metrics to a removable card for analysis.
  • Can integrate alerts or beeper outputs based on “RAD_BEEP” style signaling.
Suggested improvements and future enhancements
  • Complete power subsystem:
  • I2C compliance:
    • Add two 4.7k Resistor pull-ups to 3.3 V (size per speed/capacitance); keep traces short and avoid stubs.
  • SPI signal conditioning:
  • Decoupling audit:
    • For every IC (MCU, RTC, op-amps, and future regulators), place at least one 100nF Capacitor within 5 mm of the power pin. Add 1uF Capacitor and 10uF Capacitor nearby as bulk; observe ≤ 60% voltage derating.
  • RTC backup power:
  • Analog front end refinement:
    • Validate the photodiode biasing and choose RF1/RF2/RIN1/RIN2/C5/C6 values for target pulse bandwidth and stability; include negative-rail decoupling close to U5/U6.
  • Layout best practices:
    • Partition analog/digital grounds and return paths; place high-speed feedback loops tight; route SPI as short, matched-length where practical; keep decoupling loops minimal.
  • Scalability:
    • If write bandwidth or latency becomes limiting, consider an MCU with SDIO, more RAM, or DMA-driven buffering; add a higher-accuracy AFE or external ADC if pulse-height analysis is needed.
If you want, I can review specific subcircuits (e.g., the photodiode amplifier or the SPI/SD section) and propose concrete values and placements next.
Add I2C pull-ups
Add SPI terminations
Choose +6V regulator
Partition ground planes
Enforce decoupling placement
90 days

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how would I connect IC1 to U3?
markwuflux

markwuflux

@copilot how would I connect IC1 to U3?
2y

copilot

To connect IC1 (DS3231M+ Real-Time Clock) to U3 (STM32F030C6T6 microcontroller), you need to make the following connections:
  1. Connect the SDA pin (pin 15) of IC1 to the I2C1_SDA pin (U3:PB11) on the microcontroller.
  2. Connect the SCL pin (pin 16) of IC1 to the I2C1_SCL pin (U3:PB10) on the microcontroller.
  3. Connect the INT/SQW pin (pin 3) of IC1 to an available GPIO pin on the microcontroller, if you plan to use the interrupt/square wave output feature.
  4. Connect the ~RST pin (pin 4) of IC1 to the IC1_RST pin (U3:PA13) on the microcontroller, if you want to control the reset of the RTC from the microcontroller.
  5. Connect both the GND pin (pin 13) of IC1 and the VSS pins of U3 to the common ground.
  6. Connect the VCC pin (pin 2) and VBAT pin (pin 14) of IC1 to the +VBAT net connected to 3.3V or another suitable power supply. Ensure you have decoupling capacitors (e.g., 100nF and 10uF) close to IC1's VCC pin for power supply stability.
With these connections, the microcontroller (U3) can communicate with the Real-Time Clock (IC1) using the I2C protocol, control its reset, and make use of the interrupt/square wave output feature if needed.
2y
Is the microcontroller wired correctly?
markwuflux

markwuflux

@copilot Is the microcontroller wired correctly?
2y

copilot

Yes, the microcontroller (U3, STM32F030C6T6) appears to be wired correctly. Here are some of the connections:
  1. VDD pins are connected to the +3.3V power supply (Net 0).
  2. VSS and VSSA pins are connected to the ground (Net 4).
  3. I2C1_SCL (PB10) and I2C1_SDA (PB11) are connected to Net 9 and Net 10, respectively, for I2C communication.
  4. UART1_RX (PA10) and UART1_TX (PA9) are connected to Net 2 and Net 17, respectively, for UART communication.
  5. SPI1 signals, SCK (PA5), COPI (PA7), CIPO (PA6), and CS (PA4), are connected to their respective nets (Net 26, Net 1, Net 19, and Net 7).
Other control and monitoring pins like PA1, PA2, PA3, PA8, PA11, PA12, and PA13 are also connected appropriately. Overall, the microcontroller appears to be wired correctly based on the provided schematic.
2y
markwuflux

markwuflux

I'm worried about BOOT0, what does that do on the MCU?
2y

copilot

BOOT0 is a pin on the STM32F030C6T6 microcontroller used to select the boot mode during the startup process. By setting the BOOT0 pin state (either high or low), you can choose whether the MCU boots from its internal Flash memory, or an alternate boot source like system memory or bootloader for programming/firmware update purposes.
In the provided schematic, BOOT0 is connected to U3:PB8. For normal operation, you would generally connect BOOT0 to ground (low) so that the MCU boots from the internal Flash memory. However, if you ever need to update the firmware or use an alternate memory source, you can control the BOOT0 pin using the GPIO PB8 on the MCU. Keep in mind that this might require additional software configuration to ensure proper functionality.
2y
markwuflux

markwuflux

thanks! I'll tie it low then
2y

copilot

You're welcome! Tying BOOT0 low is a good choice for normal operation, as it ensures that the STM32F030C6T6 microcontroller boots from its internal Flash memory. If you need to update firmware or use an alternate memory source in the future, you can always modify the connections and software configuration to account for those changes. If you have any more questions or need further assistance, feel free to ask. Good luck with your project!
2y
4
I just built this circuit and I'm seeing -4V on the output of the op amp cascade...
markwuflux

markwuflux

@copilot I just built this circuit and I'm seeing -4V on the output of the op amp cascade. Any ideas what could've gone wrong?
2y

copilot

There could be several reasons for the -4V output on the op-amp cascade. Some possible causes include:
  1. Incorrect component values: Double-check the resistor and capacitor values in the circuit to ensure they match the schematic.
  2. Soldering issues: Inspect the solder joints for any shorts or cold solder joints that could affect the circuit performance.
  3. Damaged components: It's possible that one or more components, such as the op-amps, could be damaged. Verify that the components are functioning correctly.
  4. Power supply issues: Ensure that the power supply is providing the correct voltage levels to the circuit.
  5. Oscillation or instability: The op-amp cascade might be oscillating or unstable, causing unexpected output voltages. Check for proper compensation and stability.
I recommend going through these steps to identify and resolve the issue.
2y
markwuflux

markwuflux

i checked all of these and none are the problem. I'm seeing a 500kHz ripple on the output overlayed over the -4V output.
2y

copilot

If you're seeing a 500kHz ripple on the output, it could be due to oscillation or noise coupling into the circuit. Here are some suggestions to address this issue:
  1. Bypass capacitors: Ensure that proper bypass capacitors are placed close to the op-amp power supply pins to filter out high-frequency noise.
  2. Grounding and layout: Verify that the PCB layout has a proper ground plane and that the signal traces are routed away from noisy components or traces.
  3. Compensation: Check the op-amp compensation and feedback network to ensure stability. You may need to adjust the component values or add additional components to stabilize the circuit.
  4. Shielding: If the circuit is sensitive to external noise, consider adding shielding around the op-amp cascade to minimize interference.
  5. Input filtering: If the noise is coming from the input signal, consider adding a low-pass filter to the input to reduce high-frequency noise.
Investigate these areas to identify and resolve the ripple issue.
2y
markwuflux

markwuflux

what else could be causing the -4V on the output?
2y

copilot

One possible cause of the -4V output could be output voltage phase-reversal, which occurs in some op-amps when the input common-mode voltage is exceeded. This issue is typically caused when one of the internal stages of the op-amp no longer has sufficient bias voltage across it and subsequently turns off, causing the output voltage to swing to the opposite rail until the input comes back within the common-mode range. This issue is most often associated with JFET and/or BiFET amplifiers, but some bipolar single-supply amplifiers are also susceptible to it. To address this issue, you may need to ensure that the input common-mode voltage is within the specified limits for the op-amp you are using. Source
2y
5
How can I configure this op amp to get 100dB of gain with 20kHz of bandwidth whi...
markwuflux

markwuflux

@copilot How can I configure this op amp to get 100dB of gain with 20kHz of bandwidth while biasing the input at 4V?
2y

copilot

To configure the OPA847 (U5) for a gain of 100 dB (~3162 V/V) at a bandwidth of 20 kHz, you can use a two-stage approach with the input biased at 4V. Here's how you can do it:
  1. First, determine two gains to reach a total gain of 100 dB. For example, you can choose two gains of 50 dB each (316.2 V/V).
  2. For both stages, you can use a non-inverting amplifier configuration. To set the gain of each stage to 50 dB, you'll need to select appropriate resistor values for the feedback resistors Rf and Rin.
  3. The gain in a non-inverting amplifier configuration is determined by the resistors' ratio: Gain = 1 + (Rf/Rin). To get a gain of 316.2 V/V, you can choose Rf at 316.2 kΩ and Rin at 1 kΩ.
  4. To bias the input at 4V, you can create a voltage divider using two equal-value resistors (e.g., 10 kΩ) between the V+ rail (assumed to be 8V) and GND. The midpoint of the voltage divider can be AC-coupled to the non-inverting input of the first-stage op-amp using a series capacitor (e.g., using a 1 µF capacitor).
  5. The 20 kHz bandwidth can be set by a low-pass filter at the output of the second stage using an RC-filtro (Rf and Cf). The cutoff frequency is given by fc = 1 / (2π * Rf * Cf). For a 20 kHz bandwidth and using Rf = 316.2 kΩ, Cf ≈ 25 pF. You can select the nearest capacitor value available.
Note that this design assumes the OPA847 has sufficient bandwidth and can provide the required output voltage swing for your application. Be sure to check the datasheet for the specific device to ensure its performance characteristics meet your requirements.
2y
markwuflux

markwuflux

would the OPA847 have enough bandwidth to achieve 50dB of gain at 20kHz?
2y

copilot

The OPA847 has a gain-bandwidth product (GBP) of 3.9 GHz. To determine if the op-amp has sufficient bandwidth to provide 50 dB of gain at 20 kHz, you can calculate the required bandwidth for the desired gain and compare it to the GBP.
First, let's convert the gain from dB to a linear value:
Gain (linear) = 10^(Gain (dB) / 20) = 10^(50 / 20) = 316.2 V/V
Now, we can calculate the required bandwidth for the gain:
Required bandwidth = Gain * Signal bandwidth = 316.2 * 20,000 Hz = 6.324 MHz
The required bandwidth (6.324 MHz) is much lower than the OPA847's GBP (3.9 GHz), so the OPA847 should have sufficient bandwidth to achieve 50 dB of gain at 20 kHz. However, you should also ensure that the output voltage swing and other device characteristics meet your requirements by referring to the device's datasheet.
2y
markwuflux

markwuflux

thanks copilot!
2y

copilot

You're welcome, Mark! If you have any more questions or need further assistance, please don't hesitate to ask. I'm here to help!
2y
markwuflux

markwuflux

@copilot, I just noticed my rail is 6V. How would I make a voltage divider to get 4V out?
2y

copilot

To create a voltage divider that outputs 4V with a 6V input, you'll need to choose two resistors with the right ratio. The output voltage (Vout) for a voltage divider is determined by the following equation:
Vout = Vin * (R2 / (R1 + R2)),
where Vin is the input voltage (6V), R1 is the resistor connected to Vin, and R2 is the resistor connected to ground (GND). To find the ratio R2/(R1+R2) that will result in a 4V output:
R2 / (R1 + R2) = 4V / 6V = 2/3 ≈ 0.6667.
You can choose numerous resistor combinations to achieve this ratio, but some standard resistors to consider are R1 = 20 kΩ and R2 = 40 kΩ:
R2 / (R1 + R2) = 40 kΩ / (20 kΩ + 40 kΩ) = 40/60 ≈ 0.6667.
For this configuration, the output voltage will be:
Vout ≈ 6V * (40 kΩ / (20 kΩ + 40 kΩ)) ≈ 4V.
It's important to consider the input impedance of your op-amp stage so that the voltage divider output is not significantly affected. High impedance levels, typically in the MΩ range, are desirable. If necessary, use even larger resistor values for the voltage divider to achieve high input impedance while maintaining the desired ratio.
2y
markwuflux

markwuflux

How much noise is at the output if I configure the op amp for 50dB of gain
2y

copilot

To estimate the noise at the output of the op-amp configured for 50 dB of gain, you need to consider the various noise sources associated with the op-amp and the input network, such as input voltage noise, input current noise, and resistor thermal noise.
The OPA847 datasheet provides the following typical values for input voltage and current noise:
  • Input voltage noise density: 1.1 nV/√Hz
  • Input current noise density: 2.2 pA/√Hz
Assuming your input network consists of resistors RIN and RF, their thermal noise can also contribute to the overall noise. The thermal noise of a resistor can be calculated using:
Noise density = √(4 * k * T * R),
where k is Boltzmann's constant (1.38e-23 J/K), T is the temperature in Kelvin (assume room temperature, 298 K), and R is the resistance.
For RIN = 1 kΩ:
  • Thermal noise density ≈ √(4 × 1.38e-23 × 298 × 1e3) ≈ 4.07 nV/√Hz
For RF = 316.2 kΩ:
  • Thermal noise density ≈ √(4 × 1.38e-23 × 298 × 316.2e3) ≈ 22.6 nV/√Hz
The total input noise density can be estimated by adding the noise sources (op-amp and resistors) in quadrature:
Total input noise density ≈ √(1.1^2 + 4.07^2 + 22.6^2) ≈ 23.0 nV/√Hz
To get the total output noise, multiply the total input noise density by the gain:
Output noise density ≈ Gain * Total input noise density ≈ 316.2 * 23.0 nV/√Hz ≈ 7.26 µV/√Hz
To calculate the output noise over a specific bandwidth (e.g., 0 to 20 kHz), integrate the noise density over the frequency range:
Output noise (0 to 20 kHz) ≈ Output noise density * √(Bandwidth) ≈ 7.26 µV/√Hz * √(20e3) ≈ 324 µV
Keep in mind that these values are rough estimates based on typical noise densities provided in the datasheet. Actual values may vary depending on the specific device and operating conditions.
2y
8
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Environmental Radiation Logger Co-Pilot Example

Environmental Radiation Logger Co-Pilot Example
Description

Created
Last updated by markwuflux
2 Contributor(s)
markwuflux
chaykak2

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