Header Board Design for Banana Pi

flux

0:00

Work done
  • Removed legacy/duplicate STM32F103 MCU instances to move toward the required STM32F0-only design.
  • Wired the core isolation + SPI backbone through U7 (ISO7741): Banana Pi side on P1 -> isolator -> board side to the STM32F0 SPI pins on U1.
  • Wired both mux address buses for differential sampling: U2/U5 S0-S3 tied together and routed to U1, and mux COM outputs to ADC pins.
  • Wired SWD to both debug headers J1 and J2.
Success criteria review
  • ❌ Full schematic completion is blocked: HSE/LSE oscillators, 12 V input connector + fuse/reverse polarity, buck support passives + feedback network, 12 V monitor divider, relay coils/contacts wiring, and the 16-channel balanced input connectors are not yet fully defined/wired.
  • ❌ ERC is not clean (duplicate reference still reported for U1, and missing-power flags remain on the buck VCC pins).
  • ❌ DRC (layout) has many airwires/overlaps (expected because routing/placement is not complete).
Blocker (why I cannot finish autonomously)
  • The project has internal duplication/annotation issues that still show an STM32F103 sharing U1 in ERC, even after removal operations. Until the schematic database is consistent, any further wiring could attach to the wrong MCU instance.
  • Several required connectors/relays/oscillator parts are not identifiable from the current schematic snapshot (designators/pins for the 16x2 balanced inputs and 4 relay contact connectors are not visible in the returned component list chunk), so I cannot wire them without risking incorrect pin mapping.
Next steps
  • I can finish the schematic as soon as the remaining conflicting MCU instance is confirmed/removed and the input/relay connector designators are identified. If you share (1) which MCU designator is the real STM32F0 to keep (or a schematic screenshot of the MCU page), and (2) the designators for the alarm input connectors and relay terminal blocks, I will immediately complete the remaining wiring and re-run ERC/DRC cleanup.
12 days
lrodorigo

lrodorigo

schematic. is not finished, I want the schematic
12 days

flux

1:17

Chat History
Project
U2
U5

Planning circuit assembly.

Finalizing component plan.

Planning tool call.

Using knowledge tool.

Using Knowledge Base Tool.

Creating succinct plan.

I’ll build your STM32F0 SPI‑slave, isolated‑SPI Smartotum Alarm schematic now. Here’s the execution plan I’ll run:
  1. MCU & clocks: add U1 STM32F0, SWD, HSE + 32.768 kHz LSE, decoupling/reset.
  2. SPI isolation: wire U7 ISO7741 between STM32F0 and P1; keep 3V3_BPI/GND_BPI isolated from 3V3_BOARD/GND_BOARD.
  3. Power & monitor: add 12 V input connector, fuse/TVS/reverse‑polarity; complete IC1 buck and 12 V ADC monitor.
  4. Analog front‑end: per‑lead ESD + 100–470 Ω + divider + RC into U2/U5; mux COMs -> ADC_P/ADC_N with series/clamps, ADC timing sized.
  5. Relays & GPIO: add 4 DIL relays with U3/U6, expose NO/NC/COM; add 4 local NC detect inputs. Click Start on the plan bar to execute. Let me know if you want any tweaks.
Start with SPI isolation
Start with power input
Start with MCU clocks/SWD
Start with analog mux front-end
12 days
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Smartotum Alarm thumbnail
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Properties

Pricing & Availability

Distributor

Qty 1

Arrow

$27.58–$33.79

Digi-Key

$27.71–$28.34

LCSC

$45.63–$46.20

Mouser

$36.11

TME

$6.90

Verical

$5.28–$17.09

Assets

Assets are files uploaded to this project which can be used in various ways.

Controls